module jyh_4490_6_counter(Q,clk,load,in,en,upd,co);

input[3:0] in;
input en,clk,load,upd;
output reg [3:0] Q;
output reg co;

reg co_flag;

always@(posedge clk)
begin	
	if(en)
	begin	
		//同步置数
		if(load)
			begin
			Q<=in;
			co<=0;
			end
		else
		begin
			//正反计数
			if(Q>=4'd9)
				begin
				Q<=4'd0;
				co<=1;
				end
			else
				begin
				Q <= Q+1;
				co<=0;
				end
		end
	end
	else
		Q<=0;
end
endmodule

