`timescale 1ns/1ns
module jyh_4490_5_testbench;
reg clk;
reg en;
wire clk_out;
reg sel;

initial begin
	clk=0;
	sel=0;
	en=0;
	#100
	en=1;
end

always#10 clk=~clk;
always#50000000 sel=~sel;
jyh_4490_5_divider D1(
.en(en),
.sel(sel),
.clk_out(clk_out),
.clk(clk)
);
endmodule