module jyh_4490_3_counter(Q,clk,clr,load,in,en,upd,co);

input[3:0] in;
input en,clk,clr,load,upd;
output reg [3:0] Q;
output reg co;

reg co_flag;

always@(posedge clk,negedge clr)
begin

	//异步清零
	if(!clr)
		Q<=0;
	
	else if(en)
	begin	
		//同步置数
		if(load)
			begin
			Q<=in;
			end
		else if(co_flag)
		begin
			co<=1;
			co_flag=0;
		end
		else if(!co_flag)
			co<=0;
		//正反计数
		 if(upd)
			begin
				if(Q>=4'd9)
					begin
					Q<=4'd0;
					co_flag=1;
					end
				else
					begin
					Q <= Q+1;
					end
			end
		else 
			begin
				if(Q<=4'd0)
					begin
					Q<=4'd9;
					end
				else if(Q==4'd1)
					begin
					Q <= Q-1;
					co_flag=1;
					end
				else
					begin
					Q <= Q-1;
					end
			end
	end
	else
		Q<=0;
end
endmodule

