Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/UART.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
Progress: Loading Design/UART.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 21.1]
Progress: Parameterizing module clk_0
Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
Progress: Parameterizing module rs232_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem.
Info: UART: Generating UART "UART" for QUARTUS_SYNTH
Info: rs232_0: Starting Generation of RS232 UART
Error: rs232_0: The input clock frequency must be known at generation time.
Info: rs232_0: "UART" instantiated altera_up_avalon_rs232 "rs232_0"
Info: UART: Done "UART" with 2 modules, 6 files
Error: qsys-generate failed with exit code 1: 1 Error, 1 Warning
Info: Finished: Create HDL design files for synthesis
