module mstate(clk,key,out);
input clk,key;
output reg[2:0] out;
reg[1:0] state;
parameter s0=0,s1=1,s2=2;
initial begin
state=s0;
end
always @(posedge clk)
case (state)
	s0:if(key) state=s0;
		else state=s1;
	s1:if(key)	state=s1;
		else	state=s2;
	s2:if(key)	state=s2;
		else	state=s0;
	default: state=s0;
endcase

always
case (state)
	s0:out<=3'b001;
	s1:out<=3'b010;
	s2:out<=3'b100;
default:out<=3'b001;
endcase


endmodule
