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justhomework/Quartus/UART_Design/.qsys_edit/preferences.xml

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<?xml version="1.0" encoding="UTF-8"?>
<preferences>
<debug showDebugMenu="0" />
<systemtable filter="All Interfaces">
<columns>
<connections preferredWidth="79" />
<irq preferredWidth="34" />
</columns>
</systemtable>
2022-06-25 04:47:11 +00:00
<library expandedCategories="Library,Project" />
<window width="1920" height="1034" x="0" y="0" />
<hdlexample language="VERILOG" />
</preferences>