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justhomework/Quartus/v2/v2_entry_4490.v

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2022-03-29 15:03:53 +00:00
module v2_entry_4490(clk_in,enable_in,Qout,seg_out,code_out);
input clk_in,enable_in;
output wire [2:0] Qout;
output wire seg_out;
output wire [6:0]code_out;
//调用计数器模块
jyh_4490_2_1 counter(
.clk(clk_in),
.en(enable_in),
.Q(Qout));
//调用译码器模块
jyh_4490_2_2 encoder(
.in(Qout),
.out(code_out));
endmodule