justhomework/Quartus/v4/jyh_4490_4.qsf

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#
# Copyright (C) 2021  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
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# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 16:30:41  四月 12, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		jyh_4490_4_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_4_entry
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:30:41  四月 12, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name VERILOG_FILE jyh_4490_4_simpleEncoder.v
set_global_assignment -name VERILOG_FILE jyh_4490_4_entry.v
set_global_assignment -name VERILOG_FILE jyh_4490_4_encoder.v
set_global_assignment -name VERILOG_FILE jyh_4490_4_counter.v
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE jyh_4490_4_divider.v
set_location_assignment PIN_58 -to CO
set_location_assignment PIN_89 -to clk
set_location_assignment PIN_24 -to clr
set_location_assignment PIN_103 -to code[0]
set_location_assignment PIN_110 -to code[1]
set_location_assignment PIN_106 -to code[2]
set_location_assignment PIN_111 -to code[3]
set_location_assignment PIN_104 -to code[4]
set_location_assignment PIN_100 -to code[5]
set_location_assignment PIN_112 -to code[6]
set_location_assignment PIN_31 -to en
set_location_assignment PIN_32 -to in0[0]
set_location_assignment PIN_42 -to in0[1]
set_location_assignment PIN_39 -to in0[2]
set_location_assignment PIN_44 -to in0[3]
set_location_assignment PIN_33 -to load
set_location_assignment PIN_46 -to out0[0]
set_location_assignment PIN_50 -to out0[1]
set_location_assignment PIN_52 -to out0[2]
set_location_assignment PIN_54 -to out0[3]
set_location_assignment PIN_53 -to out1[1]
set_location_assignment PIN_51 -to out1[2]
set_location_assignment PIN_49 -to out1[3]
set_location_assignment PIN_119 -to seg[0]
set_location_assignment PIN_126 -to seg[1]
set_location_assignment PIN_115 -to seg[2]
set_location_assignment PIN_125 -to seg[3]
set_location_assignment PIN_114 -to seg[4]
set_location_assignment PIN_121 -to seg[5]
set_location_assignment PIN_113 -to seg[6]
set_location_assignment PIN_120 -to seg[7]
set_location_assignment PIN_30 -to upd
set_location_assignment PIN_90 -to clk_50m
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top