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justhomework/Quartus/v4/jyh_4490_4_simpleEncoder.v

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2022-04-12 08:39:06 +00:00
//七段一位译码器
module jyh_4490_4_simpleEncoder(sel,codeout,clk, d1);
input clk;
input [6:0] d1;
output reg sel; //位选
output reg [6:0] codeout; //型码
always @(clk)
begin
case (d1)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
endmodule