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justhomework/Quartus/v6/jyh_4490_6_encoder.v

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2022-05-10 09:37:13 +00:00
//七段四位译码器
module jyh_4490_4_encoder(sel,codeout,clk, d1, d2, d3, d4);
input clk;
input [6:0] d1, d2, d3, d4;
output reg [3:0] sel; //位选
output reg [6:0] codeout; //型码
//当前位置数字
reg [6:0] code_loc;
//实验性消影
reg isEnable;
reg [3:0] loc=4'b1000;
//循环移位
always @(posedge clk)
begin
if(isEnable)
isEnable<=0;
else
begin
isEnable<=1;
if(loc==4'b0001)
loc=4'b10;
else if(loc==4'b0010)
loc=4'b100;
else if(loc==4'b0100)
loc=4'b1000;
else if(loc==4'b1000)
loc=4'b1;
end
end
always @(*)
begin
if(isEnable)
begin
case (loc)
4'b0001: begin code_loc = d1; sel = 4'b0001; end
4'b0010: begin code_loc = d2; sel = 4'b0010; end
4'b0100: begin code_loc = d3; sel = 4'b0100; end
4'b1000: begin code_loc = d4; sel = 4'b1000; end
endcase
end
end
always @(*)
begin
if(isEnable)
begin
case (code_loc)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
else
codeout=7'b0;
end
endmodule