justhomework/Quartus/v6/jyh_4490_6_testbench_top.v

`timescale 1ns/1ns
module jyh_4490_6_testbench_top;
reg clk;
wire [6:0] code;
wire [7:0] seg;
wire [19:0] cnt;
reg in;
reg en;
wire subclk;
wire [3:0] out0;

initial begin
	clk=0;
	in=0;
	en=1;
end

always#10 clk=~clk;
always
begin
	#1500000;
	in=0;
	repeat(5)
	begin
		in=1;
		#1000000;
		in=0;
		#1000000;
	end
	in=1;
	#35000000
	repeat(5)
	begin
		in=0;
		#1000000;
		in=1;
		#1000000;
	end
	in=0;
	#15000000;
end
	

jyh_4490_6_entry E1(.code(code),.seg(seg),.clk_50m(clk),.en(en),.in(in),
							//数码管型码 		数码管位码    50M				清零信号 	  使能信号	 按键
								.out0(out0),.subclk(subclk),.cnt(cnt));
								
							//计数值 							消抖值
endmodule