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justhomework/Quartus/v3/jyh_4490_3_divide.v

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2022-04-09 13:38:47 +00:00
module jyh_4490_3_divide(clkin,clkout);
input clkin;
output reg clkout=0;
reg [4:0] temp;
always@(posedge clkin)
begin
temp<=temp+1;
if(temp==0)
clkout=~clkout;
end
endmodule