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justhomework/Quartus/v3/jyh_4490_3_counter.v

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2022-04-04 10:01:12 +00:00
module jyh_4490_3_counter(out,clk,clr,load,in,en,upd);
input[3:0] in;
input en,clk,clr,load,upd;
output reg [3:0] out;
always@(posedge clk,negedge clr)
begin
//异步清零
if(!clr)
out<=0;
else if(en)
begin
//同步置数
if(load)
out<=in;
//正反计数
else if(upd)
begin
if(out>=4'd9)
out=4'd0;
else
out <= out+1;
end
else
begin
if(out<=4'd0)
out=4'd9;
else
out <= out-1;
end
end
else
out<=0;
end
endmodule