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justhomework/Quartus/v6/jyh_4490_6_divider.v

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2022-05-10 09:37:13 +00:00
module jyh_4490_6_divider(clk,clk_out);
input clk;
output reg clk_out;
localparam TARGET=50000;
// localparam TARGET=1;
reg [19:0]counter=0;
initial begin
clk_out=0;
end
always @(posedge clk)
begin
counter=counter+1;
if(counter==TARGET)
begin
counter=0;
clk_out=!clk_out;
end
end
endmodule