15 lines
1.2 KiB
XML
15 lines
1.2 KiB
XML
|
<?xml version="1.0" encoding="UTF-8"?>
|
||
|
|
<preferences>
|
||
|
|
<debug showDebugMenu="0" />
|
||
|
|
<systemtable filter="All Interfaces">
|
||
|
|
<columns>
|
||
|
|
<connections preferredWidth="79" />
|
||
|
|
<irq preferredWidth="34" />
|
||
|
|
</columns>
|
||
|
|
</systemtable>
|
||
|
|
<library
|
||
|
|
expandedCategories="Library/Interface Protocols/Ethernet/Reference Design Components,Library/University Program,Library/University Program/Clock,Library/Basic Functions/Simulation; Debug and Verification/Simulation,Library/Interface Protocols/Audio & Video,Library,Project,Library/Interface Protocols/Ethernet,Library/University Program/Audio & Video,Library/Basic Functions/Bridges and Adaptors/Clock,Library/Qsys Interconnect/Interrupt,Library/Basic Functions,Library/DSP,Library/University Program/Audio & Video/Video,Library/Basic Functions/Simulation; Debug and Verification,Library/Basic Functions/Bridges and Adaptors/Memory Mapped,Library/Basic Functions/Bridges and Adaptors,Library/Qsys Interconnect/Memory-Mapped Alpha,Library/Basic Functions/Clocks; PLLs and Resets,Library/Qsys Interconnect,Library/Interface Protocols,Library/Basic Functions/On Chip Memory,Library/DSP/Video and Image Processing" />
|
||
|
|
<window width="1313" height="756" x="542" y="384" />
|
||
|
|
<hdlexample language="VERILOG" />
|
||
|
|
</preferences>
|