20 lines
1.3 KiB
Text
20 lines
1.3 KiB
Text
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component UART is
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port (
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clk_clk : in std_logic := 'X'; -- clk
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reset_reset_n : in std_logic := 'X'; -- reset_n
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rs232_0_from_uart_ready : in std_logic := 'X'; -- ready
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rs232_0_from_uart_data : out std_logic_vector(7 downto 0); -- data
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rs232_0_from_uart_error : out std_logic; -- error
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rs232_0_from_uart_valid : out std_logic; -- valid
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rs232_0_to_uart_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
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rs232_0_to_uart_error : in std_logic := 'X'; -- error
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rs232_0_to_uart_valid : in std_logic := 'X'; -- valid
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rs232_0_to_uart_ready : out std_logic; -- ready
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rs232_0_clk : in std_logic := 'X'; -- clk
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rs232_0_UART_RXD : in std_logic := 'X'; -- RXD
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rs232_0_UART_TXD : out std_logic; -- TXD
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rs232_0_reset : in std_logic := 'X' -- reset
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);
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end component UART;
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