294 lines
13 KiB
XML
294 lines
13 KiB
XML
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<?xml version="1.0" encoding="UTF-8"?>
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<deploy
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date="2022.05.24.19:47:23"
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outputDirectory="/home/ir/Documents/codelib/Quartus/Design/UART/">
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<perimeter>
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<parameter
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name="AUTO_GENERATION_ID"
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type="Integer"
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defaultValue="0"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_UNIQUE_ID"
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type="String"
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defaultValue=""
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_FAMILY"
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type="String"
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defaultValue="Cyclone IV E"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE"
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type="String"
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defaultValue="EP4CE6E22C8"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_DEVICE_SPEEDGRADE"
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type="String"
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defaultValue="8"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLK_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLK_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_CLK_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_RS232_0_CLK_CLOCK_RATE"
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type="Long"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_RS232_0_CLK_CLOCK_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<parameter
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name="AUTO_RS232_0_CLK_RESET_DOMAIN"
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type="Integer"
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defaultValue="-1"
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onHdl="0"
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affectsHdl="1" />
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<interface name="clk" kind="clock" start="0">
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<property name="clockRate" value="5000000" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="clk_clk" direction="input" role="clk" width="1" />
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</interface>
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<interface name="reset" kind="reset" start="0">
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<property name="associatedClock" value="" />
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<property name="synchronousEdges" value="NONE" />
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<port name="reset_reset_n" direction="input" role="reset_n" width="1" />
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</interface>
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<interface
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name="rs232_0_avalon_data_receive_source"
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kind="avalon_streaming"
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start="1">
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<property name="associatedClock" value="rs232_0_clk" />
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<property name="associatedReset" value="rs232_0_reset" />
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<property name="beatsPerCycle" value="1" />
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<property name="dataBitsPerSymbol" value="8" />
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<property name="emptyWithinPacket" value="false" />
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<property name="errorDescriptor" value="" />
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<property name="firstSymbolInHighOrderBits" value="true" />
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<property name="highOrderSymbolAtMSB" value="false" />
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<property name="maxChannel" value="0" />
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<property name="packetDescription" value="" />
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<property name="readyLatency" value="0" />
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<property name="symbolsPerBeat" value="1" />
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<port
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name="rs232_0_from_uart_ready"
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direction="input"
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role="ready"
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width="1" />
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<port
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name="rs232_0_from_uart_data"
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direction="output"
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role="data"
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width="8" />
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<port
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name="rs232_0_from_uart_error"
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direction="output"
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role="error"
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width="1" />
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<port
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name="rs232_0_from_uart_valid"
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direction="output"
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role="valid"
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width="1" />
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</interface>
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<interface
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name="rs232_0_avalon_data_transmit_sink"
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kind="avalon_streaming"
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start="0">
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<property name="associatedClock" value="rs232_0_clk" />
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<property name="associatedReset" value="rs232_0_reset" />
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<property name="beatsPerCycle" value="1" />
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<property name="dataBitsPerSymbol" value="8" />
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<property name="emptyWithinPacket" value="false" />
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<property name="errorDescriptor" value="" />
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<property name="firstSymbolInHighOrderBits" value="true" />
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<property name="highOrderSymbolAtMSB" value="false" />
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<property name="maxChannel" value="0" />
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<property name="packetDescription" value="" />
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<property name="readyLatency" value="0" />
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<property name="symbolsPerBeat" value="1" />
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<port name="rs232_0_to_uart_data" direction="input" role="data" width="8" />
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<port name="rs232_0_to_uart_error" direction="input" role="error" width="1" />
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<port name="rs232_0_to_uart_valid" direction="input" role="valid" width="1" />
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<port
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name="rs232_0_to_uart_ready"
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direction="output"
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role="ready"
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width="1" />
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</interface>
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<interface name="rs232_0_clk" kind="clock" start="0">
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<property name="clockRate" value="0" />
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<property name="externallyDriven" value="false" />
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<property name="ptfSchematicName" value="" />
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<port name="rs232_0_clk" direction="input" role="clk" width="1" />
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</interface>
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<interface name="rs232_0_external_interface" kind="conduit" start="0">
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<property name="associatedClock" value="" />
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<property name="associatedReset" value="" />
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<port name="rs232_0_UART_RXD" direction="input" role="RXD" width="1" />
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<port name="rs232_0_UART_TXD" direction="output" role="TXD" width="1" />
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</interface>
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<interface name="rs232_0_reset" kind="reset" start="0">
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<property name="associatedClock" value="rs232_0_clk" />
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<property name="synchronousEdges" value="DEASSERT" />
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<port name="rs232_0_reset" direction="input" role="reset" width="1" />
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</interface>
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</perimeter>
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<entity
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path=""
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parameterizationKey="UART:1.0:AUTO_CLK_CLOCK_DOMAIN=-1,AUTO_CLK_CLOCK_RATE=-1,AUTO_CLK_RESET_DOMAIN=-1,AUTO_DEVICE=EP4CE6E22C8,AUTO_DEVICE_FAMILY=Cyclone IV E,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1653392842,AUTO_RS232_0_CLK_CLOCK_DOMAIN=-1,AUTO_RS232_0_CLK_CLOCK_RATE=-1,AUTO_RS232_0_CLK_RESET_DOMAIN=-1,AUTO_UNIQUE_ID=(clock_source:21.1:clockFrequency=5000000,clockFrequencyKnown=true,inputClockFrequency=0,resetSynchronousEdges=NONE)(altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=0.0,stop_bits=1)"
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instancePathKey="UART"
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kind="UART"
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version="1.0"
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name="UART">
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<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
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<parameter name="AUTO_RS232_0_CLK_RESET_DOMAIN" value="-1" />
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<parameter name="AUTO_GENERATION_ID" value="1653392842" />
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<parameter name="AUTO_DEVICE" value="EP4CE6E22C8" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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<parameter name="AUTO_CLK_RESET_DOMAIN" value="-1" />
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<parameter name="AUTO_CLK_CLOCK_DOMAIN" value="-1" />
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<parameter name="AUTO_UNIQUE_ID" value="" />
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<parameter name="AUTO_RS232_0_CLK_CLOCK_DOMAIN" value="-1" />
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
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<parameter name="AUTO_RS232_0_CLK_CLOCK_RATE" value="-1" />
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<generatedFiles>
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/UART.v"
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type="VERILOG" />
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</generatedFiles>
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<childGeneratedFiles>
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v"
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type="VERILOG" />
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</childGeneratedFiles>
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<sourceFiles>
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<file path="/home/ir/Documents/codelib/Quartus/Design/UART.qsys" />
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</sourceFiles>
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<childSourceFiles>
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_hw.tcl" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_counters.v" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_in_deserializer.v" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_out_serializer.v" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_sync_fifo.v" />
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</childSourceFiles>
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<messages>
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<message level="Debug" culprit="UART">queue size: 0 starting:UART "UART"</message>
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<message level="Progress" culprit="min"></message>
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<message level="Progress" culprit="max"></message>
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<message level="Progress" culprit="current"></message>
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<message level="Debug">Transform: CustomInstructionTransform</message>
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<message level="Debug">No custom instruction connections, skipping transform </message>
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<message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>2</b> modules, <b>0</b> connections]]></message>
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<message level="Debug">Transform: MMTransform</message>
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<message level="Debug">Transform: InterruptMapperTransform</message>
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<message level="Debug">Transform: InterruptSyncTransform</message>
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<message level="Debug">Transform: InterruptFanoutTransform</message>
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<message level="Debug">Transform: AvalonStreamingTransform</message>
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<message level="Debug">Transform: ResetAdaptation</message>
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<message level="Debug" culprit="UART"><![CDATA["<b>UART</b>" reuses <b>altera_up_avalon_rs232</b> "<b>submodules/UART_rs232_0</b>"]]></message>
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<message level="Debug" culprit="UART">queue size: 0 starting:altera_up_avalon_rs232 "submodules/UART_rs232_0"</message>
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<message level="Info" culprit="rs232_0">Starting Generation of RS232 UART</message>
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<message level="Error" culprit="rs232_0">The input clock frequency must be known at generation time.</message>
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<message level="Info" culprit="rs232_0"><![CDATA["<b>UART</b>" instantiated <b>altera_up_avalon_rs232</b> "<b>rs232_0</b>"]]></message>
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</messages>
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</entity>
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<entity
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path="submodules/"
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parameterizationKey="altera_up_avalon_rs232:17.1:AUTO_CLK_CLOCK_RATE=0,AUTO_DEVICE_FAMILY=Cyclone IV E,avalon_bus_type=Streaming,baud=115200,data_bits=8,parity=None,ref_clk_freq=0.0,stop_bits=1"
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instancePathKey="UART:.:rs232_0"
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kind="altera_up_avalon_rs232"
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version="17.1"
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name="UART_rs232_0">
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<parameter name="baud" value="115200" />
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<parameter name="AUTO_CLK_CLOCK_RATE" value="0" />
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<parameter name="stop_bits" value="1" />
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<parameter name="ref_clk_freq" value="0.0" />
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<parameter name="avalon_bus_type" value="Streaming" />
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<parameter name="data_bits" value="8" />
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<parameter name="parity" value="None" />
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<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone IV E" />
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<generatedFiles>
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v"
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type="VERILOG" />
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<file
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path="/home/ir/Documents/codelib/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v"
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type="VERILOG" />
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</generatedFiles>
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<childGeneratedFiles/>
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<sourceFiles>
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/altera_up_avalon_rs232_hw.tcl" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_counters.v" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_in_deserializer.v" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_rs232_out_serializer.v" />
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<file
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path="/opt/intelFPGA/21.1/ip/altera/university_program/communication/altera_up_avalon_rs232/hdl/altera_up_sync_fifo.v" />
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</sourceFiles>
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<childSourceFiles/>
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<instantiator instantiator="UART" as="rs232_0" />
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<messages>
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<message level="Debug" culprit="UART">queue size: 0 starting:altera_up_avalon_rs232 "submodules/UART_rs232_0"</message>
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<message level="Info" culprit="rs232_0">Starting Generation of RS232 UART</message>
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<message level="Error" culprit="rs232_0">The input clock frequency must be known at generation time.</message>
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<message level="Info" culprit="rs232_0"><![CDATA["<b>UART</b>" instantiated <b>altera_up_avalon_rs232</b> "<b>rs232_0</b>"]]></message>
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</messages>
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</entity>
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</deploy>
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