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feat(Quartus): 最后的波纹

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This commit is contained in:
iridiumR 2022-06-13 17:46:24 +08:00
parent ad0b06f197
commit 071e18c0de
20 changed files with 1512 additions and 15 deletions
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263
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work jyh_4490_7.vo
vlog -work work Waveform.vwf.vt
vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
vcd file -direction jyh_4490_7.msim.vcd
vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work jyh_4490_7.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
vcd file -direction jyh_4490_7.msim.vcd
vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2021 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("key")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("out")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 3;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("out[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "out";
}
SIGNAL("out[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "out";
}
SIGNAL("out[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "out";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 66;
LEVEL 0 FOR 7.5;
LEVEL 1 FOR 7.5;
}
LEVEL 0 FOR 7.5;
LEVEL 1 FOR 2.5;
}
}
TRANSITION_LIST("key")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
TRANSITION_LIST("out[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("out[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("out[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "key";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "out";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
CHILDREN = 3, 4, 5;
}
DISPLAY_LINE
{
CHANNEL = "out[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "out[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "out[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 2;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

31
Quartus/final/jyh_4490_7.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 19:22:48 五月 17, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "21.1"
DATE = "19:22:48 五月 17, 2022"
# Revisions
PROJECT_REVISION = "jyh_4490_7"

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Quartus/final/jyh_4490_7.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 19:22:48 五月 17, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# jyh_4490_7_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY mstate
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:22:48 五月 17, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_location_assignment PIN_89 -to clk
set_global_assignment -name VERILOG_FILE mstate.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE tb.v
set_location_assignment PIN_24 -to key
set_location_assignment PIN_52 -to out[2]
set_location_assignment PIN_50 -to out[1]
set_location_assignment PIN_46 -to out[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

29
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module mstate(clk,key,out);
input clk,key;
output reg[2:0] out;
reg[1:0] state;
parameter s0=0,s1=1,s2=2;
initial begin
state=s0;
end
always @(posedge clk)
case (state)
s0:if(key) state=s0;
else state=s1;
s1:if(key) state=s1;
else state=s2;
s2:if(key) state=s2;
else state=s0;
default: state=s0;
endcase
always
case (state)
s0:out<=3'b001;
s1:out<=3'b010;
s2:out<=3'b100;
default:out<=3'b001;
endcase
endmodule

26
Quartus/final/tb.v Normal file
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`timescale 1ns/1ns
module tb;
reg clk;
reg key;
wire [3:0] out;
initial begin
clk=0;
key=0;
end
always#10 clk=~clk;
always begin
repeat(10)
#15 key=~key;
repeat(10)
#15 key=0;
end
mstate M1(
.clk(clk),
.key(key),
.out(out));
endmodule

15
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/home/ir/Documents/codelib/Quartus/v7/mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/mstate.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module mstate
Top level modules:
mstate
} {} {}} /home/ir/Documents/codelib/Quartus/v7/tb.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/tb.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module tb
Top level modules:
tb
} {} {}}

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Quartus/final_testbench/f.mpf Normal file
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; Copyright 1991-2009 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
; Altera Primitive libraries
;
; VHDL Section
;
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
altera = $MODEL_TECH/../altera/vhdl/altera
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
lpm = $MODEL_TECH/../altera/vhdl/220model
220model = $MODEL_TECH/../altera/vhdl/220model
maxii = $MODEL_TECH/../altera/vhdl/maxii
maxv = $MODEL_TECH/../altera/vhdl/maxv
fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
sgate = $MODEL_TECH/../altera/vhdl/sgate
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
arriav = $MODEL_TECH/../altera/vhdl/arriav
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
;
; Verilog Section
;
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
altera_ver = $MODEL_TECH/../altera/verilog/altera
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
lpm_ver = $MODEL_TECH/../altera/verilog/220model
220model_ver = $MODEL_TECH/../altera/verilog/220model
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
; Default or value of 3 or 2008 for VHDL-2008.
VHDL93 = 2002
; Show source line containing error. Default is off.
; Show_source = 1
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
; Turns on lint-style checking.
; Show_Lint = 1
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
Resolution = ps
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
; Default run length
RunLength = 100 ns
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic
; VSIM Startup command
; Startup = do startup.do
; File for saving command transcript
TranscriptFile = transcript
; File for saving command history
; CommandHistory = cmdhist.log
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
; Automatic SDF compilation
; Disables automatic compilation of SDF files in flows that support it.
; Default is on, uncomment to turn off.
; NoAutoSDFCompile = 1
[lmc]
[msg_system]
suppress = 3116
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
[Project]
** Warning: ; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 2
Project_File_0 = /home/ir/Documents/codelib/Quartus/v7/tb.v
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1654669507 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = /home/ir/Documents/codelib/Quartus/v7/mstate.v
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1654669642 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 1
Project_Sim_0 = Simulation 1
Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.tb folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {}
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
TDB_DoubleClick = Edit
TDB_CustomDoubleClick =
UPF_DoubleClick = Edit
UPF_CustomDoubleClick =
PCF_DoubleClick = Edit
PCF_CustomDoubleClick =
PROJECT_DoubleClick = Edit
PROJECT_CustomDoubleClick =
VRM_DoubleClick = Edit
VRM_CustomDoubleClick =
DEBUGDATABASE_DoubleClick = Edit
DEBUGDATABASE_CustomDoubleClick =
DEBUGARCHIVE_DoubleClick = Edit
DEBUGARCHIVE_CustomDoubleClick =
Project_Major_Version = 2020
Project_Minor_Version = 1

23
Quartus/final_testbench/transcript Normal file
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@ -0,0 +1,23 @@
# Compile of tb.v failed with 4 errors.
# Compile of tb.v failed with 2 errors.
# Compile of tb.v was successful.
vsim work.tb
# vsim work.tb
# Start time: 14:25:26 on Jun 08,2022
# Loading work.tb
# Loading work.mstate
# ** Warning: (vsim-3015) [PCDPC] - Port size (3) does not match connection size (4) for port 'out'. The port definition is at: /home/ir/Documents/codelib/Quartus/v7/mstate.v(1).
# Time: 0 ns Iteration: 0 Instance: /tb/M1 File: /home/ir/Documents/codelib/Quartus/v7/tb.v Line: 21
add wave -position end sim:/tb/clk
add wave -position end sim:/tb/key
add wave -position end sim:/tb/out
run
run
run
run
run
run
run
# Compile of mstate.v was successful.
# End time: 16:19:51 on Jun 13,2022, Elapsed time: 121:54:25
# Errors: 0, Warnings: 6

57
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@ -0,0 +1,57 @@
m255
K4
z2
!s11f vlog 2020.1 2020.02, Feb 28 2020
13
!s112 1.1
!i10d 8192
!i10e 25
!i10f 100
cModel Technology
d/home/ir
vmstate
!s110 1654669707
!i10b 1
!s100 bJ[2:DCLnjci1MRoWIG5c2
Z0 !s11b Dg1SIo80bB@j0V0VzS_@n1
IEZ8>W_cT?Ee1dN:k@1]zm3
Z1 VDg1SIo80bB@j0V0VzS_@n1
Z2 d/home/ir/Documents/codelib/Quartus/ftb
w1654669642
8/home/ir/Documents/codelib/Quartus/v7/mstate.v
F/home/ir/Documents/codelib/Quartus/v7/mstate.v
!i122 8
L0 1 29
Z3 OV;L;2020.1;71
r1
!s85 0
31
!s108 1654669707.000000
!s107 /home/ir/Documents/codelib/Quartus/v7/mstate.v|
!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v7/mstate.v|
!i113 1
Z4 o-work work
Z5 tCvgOpt 0
vtb
!s110 1654669516
!i10b 1
!s100 IFd?^70ke<Mo4QR_E_lb;3
R0
Iiee5P@OTDU^7k0NR05n=[0
R1
R2
w1654669507
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!i122 7
L0 2 25
R3
r1
!s85 0
31
!s108 1654669516.000000
!s107 /home/ir/Documents/codelib/Quartus/v7/tb.v|
!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v7/tb.v|
!i113 1
R4
R5

BIN
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4
Quartus/final_testbench/work/_vmake Normal file
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@ -0,0 +1,4 @@
m255
K4
z0
cModel Technology

7
Quartus/v6_testbench/jyh_4490_6.cr.mti
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@ -5,11 +5,4 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
jyh_4490_6_testbench
} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module jyh_4490_mstate
Top level modules:
jyh_4490_mstate
} {} {}}

4
Quartus/v6_testbench/jyh_4490_6.mpf
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@ -413,9 +413,9 @@ Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 2
Project_File_0 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652177049 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1652177049 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1652112350 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1652112350 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 1 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 1
Project_Sim_0 = Simulation 1
Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_6_testbench folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {}

10
Quartus/v6_testbench/transcript
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@ -1,7 +1,6 @@
# Compile of jyh_4490_6_testbench.v was successful.
vsim work.jyh_4490_6_testbench
# vsim work.jyh_4490_6_testbench
# Start time: 18:05:59 on May 10,2022
# Start time: 13:05:56 on Jun 08,2022
# Loading work.jyh_4490_6_testbench
# Loading work.jyh_4490_mstate
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'. Expected 5, found 4.
@ -11,10 +10,9 @@ add wave -position end sim:/jyh_4490_6_testbench/clk
add wave -position end sim:/jyh_4490_6_testbench/in
add wave -position end sim:/jyh_4490_6_testbench/en
add wave -position end sim:/jyh_4490_6_testbench/out
add wave -position end sim:/jyh_4490_6_testbench/cnt
run -continue
run -all
# Break key hit
# Simulation stop requested.
# End time: 18:28:16 on May 10,2022, Elapsed time: 0:22:17
# Errors: 0, Warnings: 6
# Break in Module jyh_4490_6_testbench at /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v line 15
# End time: 13:06:58 on Jun 08,2022, Elapsed time: 0:01:02
# Errors: 0, Warnings: 4

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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work jyh_4490_7.vo
vlog -work work Waveform.vwf.vt
vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
vcd file -direction jyh_4490_7.msim.vcd
vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work jyh_4490_7.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
vcd file -direction jyh_4490_7.msim.vcd
vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2021 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("f0")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("f1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("f2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("p")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("sta")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 1000;
LEVEL 0 FOR 0.5;
LEVEL 1 FOR 0.5;
}
}
}
TRANSITION_LIST("f0")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 20.0;
LEVEL 1 FOR 40.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 60.0;
LEVEL 1 FOR 20.0;
LEVEL 0 FOR 40.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 60.0;
LEVEL 0 FOR 30.0;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 10.0;
LEVEL 0 FOR 90.0;
LEVEL 1 FOR 30.0;
LEVEL 0 FOR 170.0;
}
}
TRANSITION_LIST("f1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("f2")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("p")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 280.0;
LEVEL 1 FOR 720.0;
}
}
TRANSITION_LIST("sta")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 660.0;
LEVEL 1 FOR 340.0;
}
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "f0";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "f1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "f2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "p";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "sta";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 19:22:48 五月 17, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "21.1"
DATE = "19:22:48 五月 17, 2022"
# Revisions
PROJECT_REVISION = "jyh_4490_7"

65
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 19:22:48 五月 17, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# jyh_4490_7_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_7_is
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:22:48 五月 17, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_FILE jyh_4490_7_is.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE jyh_4490_7_testbench.v
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_location_assignment PIN_90 -to clk
set_location_assignment PIN_23 -to f0
set_location_assignment PIN_46 -to f1
set_location_assignment PIN_50 -to f2
set_location_assignment PIN_24 -to p
set_location_assignment PIN_31 -to sta
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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module jyh_4490_7_is(f2,f1,f0,clk,p,sta);
input p,sta,f0,clk;
output reg f2,f1;
reg flag,flag2;//counter enable flag
parameter TARGET=15000; //0.3ms
parameter TARGET2=5000; //0.1ms
reg [13:0] count;//2^14=16384
reg [14:0] count2;//2^15=32768
reg negf0; //whether f0 enter low level
initial begin
flag=0;
flag2=0;
count=0;
negf0=0;
end
always@(posedge clk)
begin
if(!f0)
negf0<=1;
if(f0&&negf0)
begin
negf0<=0;
flag<=1;
flag2<=1;
f1<=1;
f2<=1;
end
else
begin
//xinchong
if(count>=TARGET)
begin
flag<=0;
f1<=0;
end
//shaochong
if(p)
begin
if(sta)
begin
if(count2>=5*TARGET2)
begin
f2<=0;
flag2<=0;
//end of a circle
end
else if(count2>=4*TARGET2)
f2<=1;
else if(count2>=3*TARGET2)
f2<=0;
else if(count2>=2*TARGET2)
f2<=1;
else if(count2>=TARGET2)
f2<=0;
end
else if(count>=3*TARGET2)
begin
f2<=0;
flag2<=0;
//end of a circle
end
else if(count>=2*TARGET2)
f2<=1;
else if(count>=TARGET2)
f2<=0;
end
else
f2<=f1;
//whether to add counter
if(flag)
count<=count+1;
else
count<=0;
if(flag2)
count2<=count2+1;
else
count2<=0;
end
end
endmodule

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`timescale 1ns/1ns
module jyh_4490_7_testbench;
wire f1,f2;
reg clk,f0,p,sta;
initial begin
clk=0;
f0=0;
p=0;
sta=0;
end
always #10 clk=~clk;
always begin
f0=1;
#300000;
f0=0;
#700000;
f0=1;
#240000;
f0=0;
#760000;
f0=1;
#180000;
f0=0;
#820000;
f0=1;
#120000;
f0=0;
#800000;
f0=1;
#60000;
f0=0;
#940000;
end
always begin
p=0;
sta=0;
#6000000;
p=1;
#3000000;
sta=1;
#3000000;
end
jyh_4490_7_is C0(
.clk(clk),
.p(p),
.f1(f1),
.f0(f0),
.sta(sta),
.f2(f2));
endmodule