From 15170f63b3bd4f2240e126d2c0f8ad05db02fa12 Mon Sep 17 00:00:00 2001 From: iridiumR Date: Wed, 18 May 2022 13:20:08 +0800 Subject: [PATCH] =?UTF-8?q?=E5=AE=9E=E9=AA=8C7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Quartus/v7/jyh_4490_7.qsf | 6 ++++++ Quartus/v7_testbench/jyh_4490_7.cr.mti | 9 ++++++++- Quartus/v7_testbench/jyh_4490_7.mpf | 2 +- Quartus/v7_testbench/transcript | 24 ++++++++++++++++++++++++ Quartus/v7_testbench/work/_info | 14 +++++++------- Quartus/v7_testbench/work/_lib1_0.qpg | Bin 24576 -> 40960 bytes 6 files changed, 46 insertions(+), 9 deletions(-) diff --git a/Quartus/v7/jyh_4490_7.qsf b/Quartus/v7/jyh_4490_7.qsf index ebec2f0..a010112 100644 --- a/Quartus/v7/jyh_4490_7.qsf +++ b/Quartus/v7/jyh_4490_7.qsf @@ -56,4 +56,10 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name VERILOG_FILE jyh_4490_7_testbench.v set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_location_assignment PIN_90 -to clk +set_location_assignment PIN_23 -to f0 +set_location_assignment PIN_46 -to f1 +set_location_assignment PIN_50 -to f2 +set_location_assignment PIN_24 -to p +set_location_assignment PIN_31 -to sta set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/v7_testbench/jyh_4490_7.cr.mti b/Quartus/v7_testbench/jyh_4490_7.cr.mti index 044659f..32f9c40 100644 --- a/Quartus/v7_testbench/jyh_4490_7.cr.mti +++ b/Quartus/v7_testbench/jyh_4490_7.cr.mti @@ -1,4 +1,11 @@ -/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v +/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module jyh_4490_7_is + +Top level modules: + jyh_4490_7_is + +} {} {}} /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module jyh_4490_7_testbench diff --git a/Quartus/v7_testbench/jyh_4490_7.mpf b/Quartus/v7_testbench/jyh_4490_7.mpf index bb15ccb..4f2cde5 100644 --- a/Quartus/v7_testbench/jyh_4490_7.mpf +++ b/Quartus/v7_testbench/jyh_4490_7.mpf @@ -413,7 +413,7 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 2 Project_File_0 = /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v -Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1652793275 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652796099 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_1 = /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652794988 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 1 diff --git a/Quartus/v7_testbench/transcript b/Quartus/v7_testbench/transcript index fd3c879..b874e3c 100644 --- a/Quartus/v7_testbench/transcript +++ b/Quartus/v7_testbench/transcript @@ -11,3 +11,27 @@ add wave -position end sim:/jyh_4490_7_testbench/f2 add wave -position end sim:/jyh_4490_7_testbench/p add wave -position end sim:/jyh_4490_7_testbench/sta run -all +# Compile of jyh_4490_7_is.v was successful. +vsim work.jyh_4490_7_testbench +# running +vsim work.jyh_4490_7_testbench +# running +vsim work.jyh_4490_7_testbench +# running +vsim work.jyh_4490_7_testbench +# running +vsim work.jyh_4490_7_testbench +# running +vsim work.jyh_4490_7_testbench +# running +vsim work.jyh_4490_7_testbench +# running +vsim work.jyh_4490_7_testbench +# running +restart -f +# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'. +# Loading work.jyh_4490_7_is +restart +run -all +# End time: 22:26:44 on May 17,2022, Elapsed time: 0:43:03 +# Errors: 0, Warnings: 1 diff --git a/Quartus/v7_testbench/work/_info b/Quartus/v7_testbench/work/_info index 9ff3101..5c6a107 100644 --- a/Quartus/v7_testbench/work/_info +++ b/Quartus/v7_testbench/work/_info @@ -10,23 +10,23 @@ z2 cModel Technology d/home/ir vjyh_4490_7_is -!s110 1652794566 +!s110 1652796112 !i10b 1 -!s100 Ch8NYc=4G@_6A9YaMMBnW2 +!s100 RiPFeLFfjmF7=E=:LFh]K1 Z0 !s11b Dg1SIo80bB@j0V0VzS_@n1 -IBT5^kcKVcE01P1:cX?C;^2 +In?ifFD9`L[n0MW4oMLaTG3 Z1 VDg1SIo80bB@j0V0VzS_@n1 Z2 d/home/ir/Documents/codelib/Quartus/v7_testbench -w1652793275 +w1652796099 8/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v F/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v -!i122 0 -L0 1 79 +!i122 3 +L0 1 89 Z3 OV;L;2020.1;71 r1 !s85 0 31 -!s108 1652794566.000000 +!s108 1652796112.000000 !s107 /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v| !s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v| !i113 1 diff --git a/Quartus/v7_testbench/work/_lib1_0.qpg b/Quartus/v7_testbench/work/_lib1_0.qpg index 2fb1b81ec020331899d3dd7f8733d3e84381a1a2..9bdb1b9eaad354bee967ed06f4ee87036924d066 100644 GIT binary patch delta 4941 zcmb7IUrbc#6~Euiu-vOOJ6F*=qu`wZ^vn^d~iXx5}m3p-JCZx4Ajc+N5duJ`In+STkZeMlXbX2)9R4jU|7D z?o|li1T-y(aetnsnQB~tF}iHz_gm!q?-h8{GI3jcL>Xa;CVJFn(F@Tn_ED$rcj6Mw z`c8_Q)Z^bR9@2#Wpm>VkHpK!7UqH}Xfde8!6M-Y5p3J;H(M3=492(1O66f&iA7Tpc zM$+@gMT{o$`$QYw4mIg9SoQ0zu$sX8DZSKNjeyX!Z|8K~Pr_(4ZXz8i1*C+j9~rIx zx6Os+XY)3p4gva7Z1iu{3h3MAHS}1-#Lmy+1%LGCmkYlZ(DG<^L0oJiBiKmif(d`6 z$fM7L6}r!mNWMNr&So5DKKz$1_7Gb>Njr8wAE1H!&bm2%fs~qE^ zhf+i5TH`sqXqqqmoO(JPy18lyE1g_zg%1J6DyCTt{X2%H&CRV$pP`=BwmA)WZceYj z!fPJ}gg8$luo?azHsh38ZHpOtvbr>IUh}_CJ$nw)5z7$M)Nk2%U$%}Ym%*HgURn-} zq9JLT3YCg8bS$*poZ+eGdE+z@+9*!Zm!VcVw5Na);g}ewH^X-PmI_CAgG?W1OFi9# z)AT^>8IRFB3_xL@{@2};XI@Sfm4%)xY#&P$HbuC8F?*{XLGV9!fR4&C3 z&91YIO-hGSL3d1raglXxN_UTXY}@En(tVbOl=LY}SCw=N5{_3pVcv0(!Vo-Sq2tq( zj96ln+9SKo`%1S)>1L#kCL=K%QqLll;su4H4t}Sijya{c#kpKCM!?ugcfpuZ4E|hb zzK=(xHQk8@Re2+n;GLUDqtTD^r7eOvSOUd1*Y5x9k zyyxbEX>=$aU-kf;P%AIL)VcaoQr?6H@(6bp5WKU_(@)Z)QcHYI&q^Dk-@vIn7jR#} z<4fOFlO!O?PsAj(mmNu-cRy(9IXsdz39a0Of08WJn8$$l03sfrI7(lX%{O+0QtK^> ztPf?|xgJQR@gBIc@w=o{*Qca&>SX$ZisUok+_0<^>W+8;l-lv4MCHc@W2|3m*~O<$Ml+UnCV~ZS8$ff{Zi=KoTtnhEg_1#f&=8@vWXQY%Uap@$8c5o>H%ay| zv!5zd>wKw}mehIqY|k8LDR(>>r|p7=CIc}5jTBkZodcr#9&3EN;6&ZWIH`tuYA4gTqU^hLtP?N`=zKM<+g&uevHNwqy7ZF2g;tu5}v@OM!8JIMaJ;LnL31D4xY zT?_0VqOW$R9wJM5+P&#|uur&F;w>c~SMuAgypwV4JmzD3n`Wz44vykH1L41(Y32D4 zP~>W#!H9UoVI`kZ@;k1)lW}-tK1Rj^VgPD9K5n){i_G&?K%-w(uQEo#g8%djx?XML z>X)guqH?9>8qKh7e(kzFoL*Mj2D7ks-4xw?Hr(Utvg^h&;z`kygeCsP^?p}z-sO59 zUDDn=D)%1#q>XOFC0W_`vi&h$|L^n!IJxU5*E4thxm(PwKrdl0r!dOB9Hh>AE2kC% z^|rv(v)+ozUR|sf@;k&h&2F*z>yKH|eKcEtHY`^kx@;|2MlD+CLW3pBIG29K>E}Mg zpCC)