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; Copyright 1991-2009 Mentor Graphics Corporation
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;
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; All Rights Reserved.
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;
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; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
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; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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;
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[Library]
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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verilog = $MODEL_TECH/../verilog
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vital2000 = $MODEL_TECH/../vital2000
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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modelsim_lib = $MODEL_TECH/../modelsim_lib
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sv_std = $MODEL_TECH/../sv_std
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; Altera Primitive libraries
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;
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; VHDL Section
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;
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altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
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altera = $MODEL_TECH/../altera/vhdl/altera
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altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
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lpm = $MODEL_TECH/../altera/vhdl/220model
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220model = $MODEL_TECH/../altera/vhdl/220model
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maxii = $MODEL_TECH/../altera/vhdl/maxii
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maxv = $MODEL_TECH/../altera/vhdl/maxv
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fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
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sgate = $MODEL_TECH/../altera/vhdl/sgate
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arriaii = $MODEL_TECH/../altera/vhdl/arriaii
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arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
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arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
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arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
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arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
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arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
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stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
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stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
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stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
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cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
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cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
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cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
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cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
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stratixv = $MODEL_TECH/../altera/vhdl/stratixv
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stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
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stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
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arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
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arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
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arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
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arriav = $MODEL_TECH/../altera/vhdl/arriav
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cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
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twentynm = $MODEL_TECH/../altera/vhdl/twentynm
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twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
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twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
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cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
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;
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; Verilog Section
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;
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altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
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altera_ver = $MODEL_TECH/../altera/verilog/altera
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altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
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lpm_ver = $MODEL_TECH/../altera/verilog/220model
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220model_ver = $MODEL_TECH/../altera/verilog/220model
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maxii_ver = $MODEL_TECH/../altera/verilog/maxii
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maxv_ver = $MODEL_TECH/../altera/verilog/maxv
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fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
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sgate_ver = $MODEL_TECH/../altera/verilog/sgate
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arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
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arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
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arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
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arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
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arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
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arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
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stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
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stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
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stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
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stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
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stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
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stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
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arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
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arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
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arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
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arriav_ver = $MODEL_TECH/../altera/verilog/arriav
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arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
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arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
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cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
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cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
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cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
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cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
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cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
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cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
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cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
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twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
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twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
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twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
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cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
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work = work
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[vcom]
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; VHDL93 variable selects language version as the default.
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; Default is VHDL-2002.
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; Value of 0 or 1987 for VHDL-1987.
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; Value of 1 or 1993 for VHDL-1993.
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; Default or value of 2 or 2002 for VHDL-2002.
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; Default or value of 3 or 2008 for VHDL-2008.
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VHDL93 = 2002
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; Show source line containing error. Default is off.
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; Show_source = 1
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; Turn off unbound-component warnings. Default is on.
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; Show_Warning1 = 0
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; Turn off process-without-a-wait-statement warnings. Default is on.
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; Show_Warning2 = 0
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; Turn off null-range warnings. Default is on.
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; Show_Warning3 = 0
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; Turn off no-space-in-time-literal warnings. Default is on.
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; Show_Warning4 = 0
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; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
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; Show_Warning5 = 0
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; Turn off optimization for IEEE std_logic_1164 package. Default is on.
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; Optimize_1164 = 0
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; Turn on resolving of ambiguous function overloading in favor of the
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; "explicit" function declaration (not the one automatically created by
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; the compiler for each type declaration). Default is off.
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; The .ini file has Explicit enabled so that std_logic_signed/unsigned
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; will match the behavior of synthesis tools.
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Explicit = 1
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; Turn off acceleration of the VITAL packages. Default is to accelerate.
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; NoVital = 1
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; Turn off VITAL compliance checking. Default is checking on.
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; NoVitalCheck = 1
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; Ignore VITAL compliance checking errors. Default is to not ignore.
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; IgnoreVitalErrors = 1
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; Turn off VITAL compliance checking warnings. Default is to show warnings.
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; Show_VitalChecksWarnings = 0
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; Keep silent about case statement static warnings.
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; Default is to give a warning.
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; NoCaseStaticError = 1
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; Keep silent about warnings caused by aggregates that are not locally static.
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; Default is to give a warning.
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; NoOthersStaticError = 1
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; Turn off inclusion of debugging info within design units.
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; Default is to include debugging info.
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; NoDebug = 1
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; Turn off "Loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on some limited synthesis rule compliance checking. Checks only:
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; -- signals used (read) by a process must be in the sensitivity list
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; CheckSynthesis = 1
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; Activate optimizations on expressions that do not involve signals,
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; waits, or function/procedure/task invocations. Default is off.
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; ScalarOpts = 1
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; Require the user to specify a configuration for all bindings,
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; and do not generate a compile time default binding for the
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; component. This will result in an elaboration error of
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; 'component not bound' if the user fails to do so. Avoids the rare
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; issue of a false dependency upon the unused default binding.
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; RequireConfigForAllDefaultBinding = 1
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; Inhibit range checking on subscripts of arrays. Range checking on
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; scalars defined with subtypes is inhibited by default.
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; NoIndexCheck = 1
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; Inhibit range checks on all (implicit and explicit) assignments to
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; scalar objects defined with subtypes.
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; NoRangeCheck = 1
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[vlog]
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; Turn off inclusion of debugging info within design units.
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; Default is to include debugging info.
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; NoDebug = 1
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; Turn off "loading..." messages. Default is messages on.
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; Quiet = 1
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; Turn on Verilog hazard checking (order-dependent accessing of global vars).
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; Default is off.
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; Hazard = 1
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; Turn on converting regular Verilog identifiers to uppercase. Allows case
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; insensitivity for module names. Default is no conversion.
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; UpCase = 1
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; Turn on incremental compilation of modules. Default is off.
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; Incremental = 1
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; Turns on lint-style checking.
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; Show_Lint = 1
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[vsim]
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; Simulator resolution
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; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
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Resolution = ps
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; User time unit for run commands
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; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
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; unit specified for Resolution. For example, if Resolution is 100ps,
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; then UserTimeUnit defaults to ps.
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; Should generally be set to default.
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UserTimeUnit = default
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; Default run length
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RunLength = 100 sec
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; Maximum iterations that can be run without advancing simulation time
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IterationLimit = 5000
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; Directive to license manager:
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; vhdl Immediately reserve a VHDL license
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; vlog Immediately reserve a Verilog license
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; plus Immediately reserve a VHDL and Verilog license
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; nomgc Do not look for Mentor Graphics Licenses
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; nomti Do not look for Model Technology Licenses
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; noqueue Do not wait in the license queue when a license isn't available
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; viewsim Try for viewer license but accept simulator license(s) instead
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; of queuing for viewer license
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; License = plus
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; Stop the simulator after a VHDL/Verilog assertion message
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; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
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BreakOnAssertion = 3
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; Assertion Message Format
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; %S - Severity Level
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; %R - Report Message
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; %T - Time of assertion
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; %D - Delta
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; %I - Instance or Region pathname (if available)
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; %% - print '%' character
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; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
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; Assertion File - alternate file for storing VHDL/Verilog assertion messages
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; AssertFile = assert.log
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; Default radix for all windows and commands...
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; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
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DefaultRadix = symbolic
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; VSIM Startup command
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; Startup = do startup.do
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; File for saving command transcript
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TranscriptFile = transcript
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; File for saving command history
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; CommandHistory = cmdhist.log
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; Specify whether paths in simulator commands should be described
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; in VHDL or Verilog format.
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; For VHDL, PathSeparator = /
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; For Verilog, PathSeparator = .
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; Must not be the same character as DatasetSeparator.
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PathSeparator = /
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; Specify the dataset separator for fully rooted contexts.
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; The default is ':'. For example, sim:/top
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; Must not be the same character as PathSeparator.
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DatasetSeparator = :
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; Disable VHDL assertion messages
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; IgnoreNote = 1
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; IgnoreWarning = 1
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; IgnoreError = 1
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; IgnoreFailure = 1
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; Default force kind. May be freeze, drive, deposit, or default
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; or in other terms, fixed, wired, or charged.
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; A value of "default" will use the signal kind to determine the
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; force kind, drive for resolved signals, freeze for unresolved signals
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; DefaultForceKind = freeze
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; If zero, open files when elaborated; otherwise, open files on
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; first read or write. Default is 0.
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; DelayFileOpen = 1
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; Control VHDL files opened for write.
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; 0 = Buffered, 1 = Unbuffered
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UnbufferedOutput = 0
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; Control the number of VHDL files open concurrently.
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; This number should always be less than the current ulimit
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; setting for max file descriptors.
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; 0 = unlimited
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ConcurrentFileLimit = 40
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; Control the number of hierarchical regions displayed as
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; part of a signal name shown in the Wave window.
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; A value of zero tells VSIM to display the full name.
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; The default is 0.
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; WaveSignalNameWidth = 0
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; Turn off warnings from the std_logic_arith, std_logic_unsigned
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; and std_logic_signed packages.
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; StdArithNoWarnings = 1
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; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
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; NumericStdNoWarnings = 1
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; Control the format of the (VHDL) FOR generate statement label
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; for each iteration. Do not quote it.
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; The format string here must contain the conversion codes %s and %d,
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; in that order, and no other conversion codes. The %s represents
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; the generate_label; the %d represents the generate parameter value
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; at a particular generate iteration (this is the position number if
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; the generate parameter is of an enumeration type). Embedded whitespace
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; is allowed (but discouraged); leading and trailing whitespace is ignored.
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; Application of the format must result in a unique scope name over all
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; such names in the design so that name lookup can function properly.
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; GenerateFormat = %s__%d
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; Specify whether checkpoint files should be compressed.
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; The default is 1 (compressed).
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; CheckpointCompressMode = 0
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; List of dynamically loaded objects for Verilog PLI applications
|
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; Veriuser = veriuser.sl
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; Specify default options for the restart command. Options can be one
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; or more of: -force -nobreakpoint -nolist -nolog -nowave
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; DefaultRestartOptions = -force
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; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
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; (> 500 megabyte memory footprint). Default is disabled.
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; Specify number of megabytes to lock.
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; LockedMemory = 1000
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|
; Turn on (1) or off (0) WLF file compression.
|
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|
; The default is 1 (compress WLF file).
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|
; WLFCompress = 0
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|
; Specify whether to save all design hierarchy (1) in the WLF file
|
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|
|
; or only regions containing logged signals (0).
|
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|
|
; The default is 0 (save only regions with logged signals).
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|
; WLFSaveAllRegions = 1
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|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
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|
|
; to the specified amount of simulation time. When the limit is exceeded
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|
; the earliest times get truncated from the file.
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|
; If both time and size limits are specified the most restrictive is used.
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|
; UserTimeUnits are used if time units are not specified.
|
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|
|
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
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|
|
; WLFTimeLimit = 0
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|
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
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|
|
; to the specified number of megabytes. If both time and size limits
|
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|
|
; are specified then the most restrictive is used.
|
|
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|
|
; The default is 0 (no limit).
|
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|
|
; WLFSizeLimit = 1000
|
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|
|
; Specify whether or not a WLF file should be deleted when the
|
|
|
|
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
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|
|
|
; The default is 0 (do not delete WLF file when simulation ends).
|
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|
|
; WLFDeleteOnQuit = 1
|
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|
|
|
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|
|
; Automatic SDF compilation
|
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|
|
; Disables automatic compilation of SDF files in flows that support it.
|
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|
|
; Default is on, uncomment to turn off.
|
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|
|
; NoAutoSDFCompile = 1
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|
[lmc]
|
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|
|
[msg_system]
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|
|
suppress = 3116
|
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|
|
; Change a message severity or suppress a message.
|
|
|
|
|
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
|
|
|
|
; Examples:
|
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|
|
; note = 3009
|
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|
|
; warning = 3033
|
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|
|
; error = 3010,3016
|
|
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|
|
; fatal = 3016,3033
|
|
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|
|
; suppress = 3009,3016,3043
|
|
|
|
|
; The command verror <msg number> can be used to get the complete
|
|
|
|
|
; description of a message.
|
|
|
|
|
|
|
|
|
|
; Control transcripting of elaboration/runtime messages.
|
|
|
|
|
; The default is to have messages appear in the transcript and
|
|
|
|
|
; recorded in the wlf file (messages that are recorded in the
|
|
|
|
|
; wlf file can be viewed in the MsgViewer). The other settings
|
|
|
|
|
; are to send messages only to the transcript or only to the
|
|
|
|
|
; wlf file. The valid values are
|
|
|
|
|
; both {default}
|
|
|
|
|
; tran {transcript only}
|
|
|
|
|
; wlf {wlf file only}
|
|
|
|
|
; msgmode = both
|
|
|
|
|
[Project]
|
|
|
|
|
** Warning: ; Warning -- Do not edit the project properties directly.
|
|
|
|
|
; Property names are dynamic in nature and property
|
|
|
|
|
; values have special syntax. Changing property data directly
|
|
|
|
|
; can result in a corrupt MPF file. All project properties
|
|
|
|
|
; can be modified through project window dialogs.
|
|
|
|
|
Project_Version = 6
|
|
|
|
|
Project_DefaultLib = work
|
|
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|
|
Project_SortMethod = unused
|
|
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|
|
Project_Files_Count = 2
|
|
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|
|
Project_File_0 = /home/ir/Documents/codelib/Quartus/v5/jyh_4490_5_divider.v
|
|
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|
|
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1650373713 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
|
|
|
|
|
Project_File_1 = /home/ir/Documents/codelib/Quartus/v5/jyh_4490_5_testbench.v
|
|
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|
|
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1650373396 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
|
|
|
|
|
Project_Sim_Count = 1
|
|
|
|
|
Project_Sim_0 = Simulation 1
|
|
|
|
|
Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_5_testbench folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {}
|
|
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|
|
Project_Folder_Count = 0
|
|
|
|
|
Echo_Compile_Output = 0
|
|
|
|
|
Save_Compile_Report = 1
|
|
|
|
|
Project_Opt_Count = 0
|
|
|
|
|
ForceSoftPaths = 0
|
|
|
|
|
ProjectStatusDelay = 5000
|
|
|
|
|
VERILOG_DoubleClick = Edit
|
|
|
|
|
VERILOG_CustomDoubleClick =
|
|
|
|
|
SYSTEMVERILOG_DoubleClick = Edit
|
|
|
|
|
SYSTEMVERILOG_CustomDoubleClick =
|
|
|
|
|
VHDL_DoubleClick = Edit
|
|
|
|
|
VHDL_CustomDoubleClick =
|
|
|
|
|
PSL_DoubleClick = Edit
|
|
|
|
|
PSL_CustomDoubleClick =
|
|
|
|
|
TEXT_DoubleClick = Edit
|
|
|
|
|
TEXT_CustomDoubleClick =
|
|
|
|
|
SYSTEMC_DoubleClick = Edit
|
|
|
|
|
SYSTEMC_CustomDoubleClick =
|
|
|
|
|
TCL_DoubleClick = Edit
|
|
|
|
|
TCL_CustomDoubleClick =
|
|
|
|
|
MACRO_DoubleClick = Edit
|
|
|
|
|
MACRO_CustomDoubleClick =
|
|
|
|
|
VCD_DoubleClick = Edit
|
|
|
|
|
VCD_CustomDoubleClick =
|
|
|
|
|
SDF_DoubleClick = Edit
|
|
|
|
|
SDF_CustomDoubleClick =
|
|
|
|
|
XML_DoubleClick = Edit
|
|
|
|
|
XML_CustomDoubleClick =
|
|
|
|
|
LOGFILE_DoubleClick = Edit
|
|
|
|
|
LOGFILE_CustomDoubleClick =
|
|
|
|
|
UCDB_DoubleClick = Edit
|
|
|
|
|
UCDB_CustomDoubleClick =
|
|
|
|
|
TDB_DoubleClick = Edit
|
|
|
|
|
TDB_CustomDoubleClick =
|
|
|
|
|
UPF_DoubleClick = Edit
|
|
|
|
|
UPF_CustomDoubleClick =
|
|
|
|
|
PCF_DoubleClick = Edit
|
|
|
|
|
PCF_CustomDoubleClick =
|
|
|
|
|
PROJECT_DoubleClick = Edit
|
|
|
|
|
PROJECT_CustomDoubleClick =
|
|
|
|
|
VRM_DoubleClick = Edit
|
|
|
|
|
VRM_CustomDoubleClick =
|
|
|
|
|
DEBUGDATABASE_DoubleClick = Edit
|
|
|
|
|
DEBUGDATABASE_CustomDoubleClick =
|
|
|
|
|
DEBUGARCHIVE_DoubleClick = Edit
|
|
|
|
|
DEBUGARCHIVE_CustomDoubleClick =
|
|
|
|
|
Project_Major_Version = 2020
|
|
|
|
|
Project_Minor_Version = 1
|
iridiumR