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实验5小修改

This commit is contained in:
iridiumR 2022-04-19 22:26:41 +08:00
parent f370f07eee
commit 1faf39cfce
6 changed files with 37 additions and 37 deletions
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4
.gitignore vendored
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@ -101,7 +101,7 @@ Thumbs.db
# Quartus
# Quartus/ModelSim
*_generation_script*
*_inst.vhd
*.bak
@ -114,3 +114,5 @@ Thumbs.db
PLLJ_PLLSPE_INFO.txt
*.qws
*.qdb
*.wlf
*.qtl

6
Quartus/v5/jyh_4490_5.qsf
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@ -54,4 +54,8 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE jyh_4490_5_testbench.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_location_assignment PIN_90 -to clk
set_location_assignment PIN_46 -to clk_out
set_location_assignment PIN_24 -to en
set_location_assignment PIN_31 -to sel

7
Quartus/v5_testbench/jyh_4490_5_testbench.cr.mti
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@ -5,4 +5,11 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb
Top level modules:
jyh_4490_5_divider
} {} {}} /home/ir/Documents/codelib/Quartus/v5/jyh_4490_5_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v5/jyh_4490_5_testbench.v
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
-- Compiling module jyh_4490_5_testbench
Top level modules:
jyh_4490_5_testbench
} {} {}}

4
Quartus/v5_testbench/jyh_4490_5_testbench.mpf
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@ -413,9 +413,9 @@ Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 2
Project_File_0 = /home/ir/Documents/codelib/Quartus/v5/jyh_4490_5_divider.v
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1650373713 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1650375953 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = /home/ir/Documents/codelib/Quartus/v5/jyh_4490_5_testbench.v
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1650373396 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1650375953 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 1
Project_Sim_0 = Simulation 1
Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_5_testbench folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {}

13
Quartus/v5_testbench/transcript
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@ -1,13 +0,0 @@
# Compile of jyh_4490_5_divider.v was successful.
vsim work.jyh_4490_5_testbench
# vsim work.jyh_4490_5_testbench
# Start time: 21:31:49 on Apr 19,2022
# Loading work.jyh_4490_5_testbench
# Loading work.jyh_4490_5_divider
add wave -position end sim:/jyh_4490_5_testbench/clk
add wave -position end sim:/jyh_4490_5_testbench/en
add wave -position end sim:/jyh_4490_5_testbench/sel
add wave -position end sim:/jyh_4490_5_testbench/clk_out
run -continue
run -all
run

40
Quartus/v5_testbench/work/_info
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@ -10,48 +10,48 @@ z2
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