From 2136c9522514480831f3cf79686a7111147dbd7d Mon Sep 17 00:00:00 2001 From: iridiumR Date: Tue, 12 Apr 2022 17:03:50 +0800 Subject: [PATCH] =?UTF-8?q?=E5=AE=9E=E9=AA=8C=E6=80=A7=E4=BB=A3=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Quartus/v4/Waveform.vwf | 1310 +++++++++++++++++++++++++++ Quartus/v4/greybox_tmp/cbx_args.txt | 61 ++ Quartus/v4/jyh_4490_4.qsf | 2 + Quartus/v4/jyh_4490_4_divider.v | 18 + Quartus/v4/jyh_4490_4_encoder.v | 24 +- Quartus/v4/jyh_4490_4_entry.v | 37 +- 6 files changed, 1419 insertions(+), 33 deletions(-) create mode 100644 Quartus/v4/Waveform.vwf create mode 100644 Quartus/v4/greybox_tmp/cbx_args.txt create mode 100644 Quartus/v4/jyh_4490_4_divider.v diff --git a/Quartus/v4/Waveform.vwf b/Quartus/v4/Waveform.vwf new file mode 100644 index 0000000..2428555 --- /dev/null +++ b/Quartus/v4/Waveform.vwf @@ -0,0 +1,1310 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_4 -c jyh_4490_4 --vector_source="/home/ir/Documents/codelib/Quartus/v4/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v4/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_4 -c jyh_4490_4 --vector_source="/home/ir/Documents/codelib/Quartus/v4/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v4/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v4/simulation/qsim/" jyh_4490_4 -c jyh_4490_4 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v4/simulation/qsim/" jyh_4490_4 -c jyh_4490_4 +onerror {exit -code 1} +vlib work +vlog -work work jyh_4490_4.vo +vlog -work work Waveform.vwf.vt +vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_4_entry_vlg_vec_tst +vcd file -direction jyh_4490_4.msim.vcd +vcd add -internal jyh_4490_4_entry_vlg_vec_tst/* +vcd add -internal jyh_4490_4_entry_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + + +onerror {exit -code 1} +vlib work +vlog -work work jyh_4490_4.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_4_entry_vlg_vec_tst +vcd file -direction jyh_4490_4.msim.vcd +vcd add -internal jyh_4490_4_entry_vlg_vec_tst/* +vcd add -internal jyh_4490_4_entry_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2021 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("CO") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clr") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("code") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("code[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("en") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in0[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in0"; +} + +SIGNAL("in0[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in0"; +} + +SIGNAL("in0[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in0"; +} + +SIGNAL("in0[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in0"; +} + +SIGNAL("in1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in1[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in1"; +} + +SIGNAL("in1[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in1"; +} + +SIGNAL("in1[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in1"; +} + +SIGNAL("in1[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "in1"; +} + +SIGNAL("load") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("out0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("out0[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("out0[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("out0[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("out0[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("out1") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("out1[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out1"; +} + +SIGNAL("out1[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out1"; +} + +SIGNAL("out1[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out1"; +} + +SIGNAL("out1[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out1"; +} + +SIGNAL("sel") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("sel[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("sel[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("sel[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("sel[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("sel[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("sel[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("sel[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("sel[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sel"; +} + +SIGNAL("upd") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("subclk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +TRANSITION_LIST("CO") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 200; + LEVEL 0 FOR 2.5; + LEVEL 1 FOR 2.5; + } + } +} + +TRANSITION_LIST("clr") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("code[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("en") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 960.0; + } +} + +TRANSITION_LIST("in0[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("in0[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("in0[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("in0[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("in1[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("in1[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("in1[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("in1[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("load") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("out0[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out0[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out0[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out0[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out1[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out1[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out1[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out1[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sel[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("upd") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 500.0; + LEVEL 1 FOR 500.0; + } +} + +TRANSITION_LIST("subclk") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clr"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "subclk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "en"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "CO"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "code"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; + CHILDREN = 6, 7, 8, 9, 10, 11, 12; +} + +DISPLAY_LINE +{ + CHANNEL = "code[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "code[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "code[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "code[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "code[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "code[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "code[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "in0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 0; + CHILDREN = 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "in0[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "in0[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "in0[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "in0[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "in1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; + CHILDREN = 19, 20, 21, 22; +} + +DISPLAY_LINE +{ + CHANNEL = "in1[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "in1[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "in1[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "in1[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "load"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "out0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 24; + TREE_LEVEL = 0; + CHILDREN = 25, 26, 27, 28; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 28; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "out1"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 29; + TREE_LEVEL = 0; + CHILDREN = 30, 31, 32, 33; +} + +DISPLAY_LINE +{ + CHANNEL = "out1[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 30; + TREE_LEVEL = 1; + PARENT = 29; +} + +DISPLAY_LINE +{ + CHANNEL = "out1[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 31; + TREE_LEVEL = 1; + PARENT = 29; +} + +DISPLAY_LINE +{ + CHANNEL = "out1[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 32; + TREE_LEVEL = 1; + PARENT = 29; +} + +DISPLAY_LINE +{ + CHANNEL = "out1[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 33; + TREE_LEVEL = 1; + PARENT = 29; +} + +DISPLAY_LINE +{ + CHANNEL = "sel"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 34; + TREE_LEVEL = 0; + CHILDREN = 35, 36, 37, 38, 39, 40, 41, 42; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 35; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 36; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 37; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 38; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 39; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 40; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 41; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "sel[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 42; + TREE_LEVEL = 1; + PARENT = 34; +} + +DISPLAY_LINE +{ + CHANNEL = "upd"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 43; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Quartus/v4/greybox_tmp/cbx_args.txt b/Quartus/v4/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..fbc3e48 --- /dev/null +++ b/Quartus/v4/greybox_tmp/cbx_args.txt @@ -0,0 +1,61 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=1 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=1 +CLK0_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=166666 +INTENDED_DEVICE_FAMILY="Cyclone IV E" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_USED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_USED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_UNUSED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +SELF_RESET_ON_LOSS_LOCK=OFF +WIDTH_CLOCK=5 +DEVICE_FAMILY="Cyclone IV E" +CBX_AUTO_BLACKBOX=ALL +areset +inclk +inclk +clk +locked diff --git a/Quartus/v4/jyh_4490_4.qsf b/Quartus/v4/jyh_4490_4.qsf index bd67149..73e6fa4 100644 --- a/Quartus/v4/jyh_4490_4.qsf +++ b/Quartus/v4/jyh_4490_4.qsf @@ -55,4 +55,6 @@ set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE jyh_4490_4_divider.v +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/v4/jyh_4490_4_divider.v b/Quartus/v4/jyh_4490_4_divider.v new file mode 100644 index 0000000..2af85c0 --- /dev/null +++ b/Quartus/v4/jyh_4490_4_divider.v @@ -0,0 +1,18 @@ +module jyh_4490_4_divider(clk,clk_out); + input clk; + output reg clk_out; + localparam TARGET=2; + reg [15:0]counter=0; + initial begin + clk_out=0; + end + always @(posedge clk) + begin + counter=counter+1; + if(counter==TARGET) + begin + counter=0; + clk_out=!clk_out; + end + end +endmodule \ No newline at end of file diff --git a/Quartus/v4/jyh_4490_4_encoder.v b/Quartus/v4/jyh_4490_4_encoder.v index c4ec319..333571f 100644 --- a/Quartus/v4/jyh_4490_4_encoder.v +++ b/Quartus/v4/jyh_4490_4_encoder.v @@ -1,8 +1,8 @@ //七段四位译码器 -module jyh_4490_4_encoder(sel,codeout,clk, d1, d2); +module jyh_4490_4_encoder(sel,codeout,clk, d1, d2, d3, d4); input clk; -input [6:0] d1, d2; -output reg [1:0] sel; //位选 +input [6:0] d1, d2, d3, d4; +output reg [3:0] sel; //位选 output reg [6:0] codeout; //型码 @@ -21,10 +21,14 @@ begin else begin isEnable<=1; - if(loc==2'b01) - loc=2'b10; - else - loc=2'b01; + if(loc==4'b01) + loc=4'b10; + else if(loc==4'b10) + loc=4'b100; + else if(loc==4'b100) + loc=4'b1000; + else if(loc==4'b1000) + loc=4'b1; end end @@ -33,8 +37,10 @@ begin if(isEnable) begin case (loc) - 2'b01: begin code_loc = d1; sel = 4'b10; end - 2'b10: begin code_loc = d2; sel = 4'b01; end + 4'b0001: begin code_loc = d1; sel = 4'b0001; end + 4'b0010: begin code_loc = d2; sel = 4'b0010; end + 4'b0100: begin code_loc = d2; sel = 4'b0100; end + 4'b1000: begin code_loc = d2; sel = 4'b1000; end endcase end end diff --git a/Quartus/v4/jyh_4490_4_entry.v b/Quartus/v4/jyh_4490_4_entry.v index 28ec88e..c9507c2 100644 --- a/Quartus/v4/jyh_4490_4_entry.v +++ b/Quartus/v4/jyh_4490_4_entry.v @@ -1,7 +1,7 @@ module jyh_4490_4_entry(out1, out0, code, sel, CO, // 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位 - in1, in0, load, clk, clr, en, upd); - // 十位装载 个位装载 装载信号 计数时钟信号 清零信号 使能信号 正反计数标志位 + in1, in0, load, clk, subclk, clr, en, upd); + // 十位装载 个位装载 装载信号 计数时钟信号 分频信号 清零信号 使能信号 正反计数标志位 output [3:0] out1; output [3:0] out0; @@ -13,17 +13,17 @@ input [3:0] in0; input clk,load,clr,en,upd; -//wire subclk; -//jyh_4490_3_divide( -//.clkin(clk), -//.clkout(subclk) -//); +output subclk; +jyh_4490_4_divider D1( +.clk(clk), +.clk_out(subclk) +); //个位计数器 -jyh_4490_4_counter c0( +jyh_4490_4_counter C1( .Q(out0), -.clk(clk), +.clk(subclk), .co(CO), .clr(clr), .load(load), @@ -32,31 +32,20 @@ jyh_4490_4_counter c0( .upd(upd)); //十位计数器 -jyh_4490_4_counter c1( +jyh_4490_4_counter C2( .Q(out1), .clk(CO||load), .clr(clr), .load(load), -.in(in1), .en(en), .upd(upd)); - - //四位数码管译码器 -//jyh_4490_3_encoder e1( -//.codeout(code), -//.d1(out0), -//.d2(out1), -//.clk(clk), -//.sel(sel[1:0]) -//); - -jyh_4490_4_simpleEncoder e1( +jyh_4490_4_encoder E1( .codeout(code), .d1(out0), +.d2(out1), .clk(clk), -.sel(sel[0:0]) +.sel(sel[3:0]) ); - endmodule