From 25530c5d7c0c8a903173841ddb1d0d82cb0a2fac Mon Sep 17 00:00:00 2001 From: iridiumR Date: Sat, 9 Apr 2022 21:38:47 +0800 Subject: [PATCH] =?UTF-8?q?=E8=BF=98=E5=9C=A8=E6=94=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Quartus/v3/Waveform.vwf | 29 ++++++----------------------- Quartus/v3/jyh_4490_3.qsf | 23 ++++++++++++++++++++--- Quartus/v3/jyh_4490_3_counter.v | 22 +++++++++++++++------- Quartus/v3/jyh_4490_3_divide.v | 12 ++++++++++++ Quartus/v3/jyh_4490_3_encoder.v | 6 +++--- Quartus/v3/jyh_4490_3_entry.v | 16 +++++++++++++--- 6 files changed, 69 insertions(+), 39 deletions(-) create mode 100644 Quartus/v3/jyh_4490_3_divide.v diff --git a/Quartus/v3/Waveform.vwf b/Quartus/v3/Waveform.vwf index 7059732..5681c56 100644 --- a/Quartus/v3/Waveform.vwf +++ b/Quartus/v3/Waveform.vwf @@ -7,7 +7,7 @@ vlib work vlog -work work jyh_4490_3.vo vlog -work work Waveform.vwf.vt -vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_entry_vlg_vec_tst +vsim -voptargs=+acc -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_entry_vlg_vec_tst vcd file -direction jyh_4490_3.msim.vcd vcd add -internal jyh_4490_3_entry_vlg_vec_tst/* vcd add -internal jyh_4490_3_entry_vlg_vec_tst/i1/* @@ -21,12 +21,6 @@ after 2500 simTimestamp run -all quit -f - - - - - - onerror {exit -code 1} vlib work @@ -46,12 +40,6 @@ after 2500 simTimestamp run -all quit -f - - - - - - verilog */ @@ -489,9 +477,7 @@ TRANSITION_LIST("clr") NODE { REPEAT = 1; - LEVEL 1 FOR 260.0; - LEVEL 0 FOR 30.0; - LEVEL 1 FOR 710.0; + LEVEL 1 FOR 1000.0; } } @@ -500,8 +486,7 @@ TRANSITION_LIST("en") NODE { REPEAT = 1; - LEVEL 0 FOR 20.0; - LEVEL 1 FOR 980.0; + LEVEL 1 FOR 1000.0; } } @@ -582,9 +567,7 @@ TRANSITION_LIST("load") NODE { REPEAT = 1; - LEVEL 0 FOR 370.0; - LEVEL 1 FOR 20.0; - LEVEL 0 FOR 610.0; + LEVEL 0 FOR 1000.0; } } @@ -665,8 +648,8 @@ TRANSITION_LIST("upd") NODE { REPEAT = 1; - LEVEL 0 FOR 150.0; - LEVEL 1 FOR 850.0; + LEVEL 0 FOR 500.0; + LEVEL 1 FOR 500.0; } } diff --git a/Quartus/v3/jyh_4490_3.qsf b/Quartus/v3/jyh_4490_3.qsf index 7dcb37d..710d079 100644 --- a/Quartus/v3/jyh_4490_3.qsf +++ b/Quartus/v3/jyh_4490_3.qsf @@ -88,6 +88,23 @@ set_location_assignment PIN_111 -to code[3] set_location_assignment PIN_106 -to code[2] set_location_assignment PIN_110 -to code[1] set_location_assignment PIN_103 -to code[0] -set_location_assignment PIN_126 -to sel[1] -set_location_assignment PIN_119 -to sel[0] -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_location_assignment PIN_119 -to sel[1] +set_location_assignment PIN_126 -to sel[0] +set_location_assignment PIN_115 -to sel[2] +set_location_assignment PIN_125 -to sel[3] +set_location_assignment PIN_114 -to sel[4] +set_location_assignment PIN_121 -to sel[5] +set_location_assignment PIN_113 -to sel[6] +set_location_assignment PIN_120 -to sel[7] +set_global_assignment -name VERILOG_FILE jyh_4490_3_divide.v +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Precision Synthesis" +set_global_assignment -name EDA_LMF_FILE mentor.lmf -section_id eda_design_synthesis +set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis +set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan \ No newline at end of file diff --git a/Quartus/v3/jyh_4490_3_counter.v b/Quartus/v3/jyh_4490_3_counter.v index ff912e2..226bb70 100644 --- a/Quartus/v3/jyh_4490_3_counter.v +++ b/Quartus/v3/jyh_4490_3_counter.v @@ -5,6 +5,7 @@ input en,clk,clr,load,upd; output reg [3:0] Q; output reg co; +reg co_flag; always@(posedge clk,negedge clr) begin @@ -19,21 +20,25 @@ begin if(load) begin Q<=in; - co<=1'b1; end - + else if(co_flag) + begin + co<=1; + co_flag=0; + end + else if(!co_flag) + co<=0; //正反计数 - else if(upd) + if(upd) begin if(Q>=4'd9) begin Q<=4'd0; - co<=1'b1; + co_flag=1; end else begin Q <= Q+1; - co<=0; end end else @@ -41,12 +46,15 @@ begin if(Q<=4'd0) begin Q<=4'd9; - co<=1'b1; + end + else if(Q==4'd1) + begin + Q <= Q-1; + co_flag=1; end else begin Q <= Q-1; - co<=0; end end end diff --git a/Quartus/v3/jyh_4490_3_divide.v b/Quartus/v3/jyh_4490_3_divide.v new file mode 100644 index 0000000..acf6b05 --- /dev/null +++ b/Quartus/v3/jyh_4490_3_divide.v @@ -0,0 +1,12 @@ +module jyh_4490_3_divide(clkin,clkout); +input clkin; +output reg clkout=0; + +reg [4:0] temp; +always@(posedge clkin) +begin +temp<=temp+1; +if(temp==0) +clkout=~clkout; +end +endmodule \ No newline at end of file diff --git a/Quartus/v3/jyh_4490_3_encoder.v b/Quartus/v3/jyh_4490_3_encoder.v index 199d7a8..c5e9f52 100644 --- a/Quartus/v3/jyh_4490_3_encoder.v +++ b/Quartus/v3/jyh_4490_3_encoder.v @@ -1,8 +1,8 @@ //七段四位译码器 -module jyh_4490_3_encoder(sel,codeout,clk, d1, d2, d3, d4); +module jyh_4490_3_encoder(sel,codeout,clk, d1, d2); input clk; -input [6:0] d1, d2, d3, d4; -output reg [3:0] sel; //位选 +input [6:0] d1, d2; +output reg [1:0] sel; //位选 output reg [6:0] codeout; //型码 diff --git a/Quartus/v3/jyh_4490_3_entry.v b/Quartus/v3/jyh_4490_3_entry.v index c685be1..7beffe9 100644 --- a/Quartus/v3/jyh_4490_3_entry.v +++ b/Quartus/v3/jyh_4490_3_entry.v @@ -6,12 +6,20 @@ module jyh_4490_3_entry(out1, out0, code, sel, CO, output [3:0] out1; output [3:0] out0; output [6:0] code; -output [1:0] sel; +output [7:0] sel; output CO; input [3:0] in1; input [3:0] in0; input clk,load,clr,en,upd,clk2; + +wire subclk; +jyh_4490_3_divide( +.clkin(clk), +.clkout(subclk) +); + + //个位计数器 jyh_4490_3_counter c0( .Q(out0), @@ -26,20 +34,22 @@ jyh_4490_3_counter c0( //十位计数器 jyh_4490_3_counter c1( .Q(out1), -.clk(CO), +.clk(CO||load), .clr(clr), .load(load), .in(in1), .en(en), .upd(upd)); + + //四位数码管译码器 jyh_4490_3_encoder e1( .codeout(code), .d1(out0), .d2(out1), .clk(clk2), -.sel(sel) +.sel(sel[1:0]) ); endmodule