From 2b2e294e7946aa29e32f0129435f1697d5ef3181 Mon Sep 17 00:00:00 2001 From: iridiumR Date: Tue, 10 May 2022 18:11:28 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A4=A7=E6=A6=82=E6=98=AF=E5=AF=B9=E7=9A=84?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Quartus/v6/Waveform.vwf | 842 +++++++++++++++++++ Quartus/v6/jyh_4490_6.qsf | 5 +- Quartus/v6/jyh_4490_6_counter.v | 15 +- Quartus/v6/jyh_4490_6_entry.v | 24 +- Quartus/v6/jyh_4490_6_testbench.v | 4 +- Quartus/v6/jyh_4490_6_testbench_top.v | 7 +- Quartus/v6_testbench/jyh_4490_6.cr.mti | 9 +- Quartus/v6_testbench/jyh_4490_6.mpf | 4 +- Quartus/v6_testbench/transcript | 84 +- Quartus/v6_testbench/work/_info | 42 +- Quartus/v6_testbench/work/_lib1_0.qpg | Bin 24576 -> 32768 bytes Quartus/v6_testbench_top/jyh_4490_top.cr.mti | 14 +- Quartus/v6_testbench_top/jyh_4490_top.mpf | 20 +- Quartus/v6_testbench_top/transcript | 40 +- Quartus/v6_testbench_top/work/_info | 52 +- Quartus/v6_testbench_top/work/_lib1_0.qpg | Bin 98304 -> 0 bytes Quartus/v6_testbench_top/work/_lib1_1.qpg | Bin 0 -> 106496 bytes 17 files changed, 947 insertions(+), 215 deletions(-) create mode 100644 Quartus/v6/Waveform.vwf delete mode 100644 Quartus/v6_testbench_top/work/_lib1_0.qpg create mode 100644 Quartus/v6_testbench_top/work/_lib1_1.qpg diff --git a/Quartus/v6/Waveform.vwf b/Quartus/v6/Waveform.vwf new file mode 100644 index 0000000..39d9060 --- /dev/null +++ b/Quartus/v6/Waveform.vwf @@ -0,0 +1,842 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_6 -c jyh_4490_6 --vector_source="/home/ir/Documents/codelib/Quartus/v6/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v6/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_6 -c jyh_4490_6 --vector_source="/home/ir/Documents/codelib/Quartus/v6/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v6/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v6/simulation/qsim/" jyh_4490_6 -c jyh_4490_6 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v6/simulation/qsim/" jyh_4490_6 -c jyh_4490_6 +onerror {exit -code 1} +vlib work +vlog -work work jyh_4490_6.vo +vlog -work work Waveform.vwf.vt +vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_6_entry_vlg_vec_tst +vcd file -direction jyh_4490_6.msim.vcd +vcd add -internal jyh_4490_6_entry_vlg_vec_tst/* +vcd add -internal jyh_4490_6_entry_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + +onerror {exit -code 1} +vlib work +vlog -work work jyh_4490_6.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_6_entry_vlg_vec_tst +vcd file -direction jyh_4490_6.msim.vcd +vcd add -internal jyh_4490_6_entry_vlg_vec_tst/* +vcd add -internal jyh_4490_6_entry_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2021 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk_50m") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("clr") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("code") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("code[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("code[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "code"; +} + +SIGNAL("en") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("in") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("out0") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("out0[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("out0[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("out0[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("out0[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "out0"; +} + +SIGNAL("seg") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 8; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("seg[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("seg[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("seg[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("seg[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("seg[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("seg[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("seg[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("seg[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "seg"; +} + +SIGNAL("subclk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk_50m") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("clr") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("code[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("code[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("en") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("in") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("out0[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out0[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out0[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("out0[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("seg[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("subclk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 100; + LEVEL 0 FOR 5.0; + LEVEL 1 FOR 5.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "subclk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clk_50m"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "clr"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "code"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7, 8, 9, 10; +} + +DISPLAY_LINE +{ + CHANNEL = "code[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "code[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "code[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "code[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "code[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "code[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "code[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "en"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "in"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "out0"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 0; + CHILDREN = 14, 15, 16, 17; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "out0[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 13; +} + +DISPLAY_LINE +{ + CHANNEL = "seg"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; + CHILDREN = 19, 20, 21, 22, 23, 24, 25, 26; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 18; +} + +DISPLAY_LINE +{ + CHANNEL = "seg[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 18; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Quartus/v6/jyh_4490_6.qsf b/Quartus/v6/jyh_4490_6.qsf index 45f47a4..c759d36 100644 --- a/Quartus/v6/jyh_4490_6.qsf +++ b/Quartus/v6/jyh_4490_6.qsf @@ -57,5 +57,6 @@ set_global_assignment -name VERILOG_FILE jyh_4490_6_testbench_top.v set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name VERILOG_FILE jyh_4490_6_divider.v \ No newline at end of file +set_global_assignment -name VERILOG_FILE jyh_4490_6_divider.v +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/v6/jyh_4490_6_counter.v b/Quartus/v6/jyh_4490_6_counter.v index ef8f710..4cf607b 100644 --- a/Quartus/v6/jyh_4490_6_counter.v +++ b/Quartus/v6/jyh_4490_6_counter.v @@ -1,20 +1,15 @@ -module jyh_4490_6_counter(Q,clk,clr,load,in,en,upd,co); +module jyh_4490_6_counter(Q,clk,load,in,en,upd,co); input[3:0] in; -input en,clk,clr,load,upd; +input en,clk,load,upd; output reg [3:0] Q; output reg co; reg co_flag; -always@(posedge clk,negedge clr) -begin - - //异步清零 - if(!clr) - Q<=0; - - else if(en) +always@(posedge clk) +begin + if(en) begin //同步置数 if(load) diff --git a/Quartus/v6/jyh_4490_6_entry.v b/Quartus/v6/jyh_4490_6_entry.v index 2a243b1..0923729 100644 --- a/Quartus/v6/jyh_4490_6_entry.v +++ b/Quartus/v6/jyh_4490_6_entry.v @@ -1,16 +1,15 @@ -module jyh_4490_6_entry(code, seg, clk_50m, clr, en, in, - //数码管型码 数码管位码 50M 清零信号 使能信号 按键 - out0, out1, subclk); - //计数值 消抖值 +module jyh_4490_6_entry(code, seg, clk_50m, en, in, + //数码管型码 数码管位码 50M 使能信号 按键 + out0, subclk); + //计数值 消抖值 output [6:0] code; output [7:0] seg; -input clr,en,clk_50m,in; +input en,clk_50m,in; output subclk; output [3:0] out0; -output [3:0] out1; -wire CO; + wire freshclk; reg upd; @@ -29,16 +28,6 @@ jyh_4490_6_divider D1( jyh_4490_6_counter C1( .Q(out0), .clk(subclk), -.co(CO), -.clr(clr), -.en(en), -.upd(upd)); - -//十位计数器 -jyh_4490_6_counter C2( -.Q(out1), -.clk(CO||(subclk)), -.clr(clr), .en(en), .upd(upd)); @@ -46,7 +35,6 @@ jyh_4490_6_counter C2( jyh_4490_4_encoder E1( .codeout(code), .d1(out0), -.d2(out1), .clk(freshclk), .sel(seg[3:0]) ); diff --git a/Quartus/v6/jyh_4490_6_testbench.v b/Quartus/v6/jyh_4490_6_testbench.v index 64a672b..14f6954 100644 --- a/Quartus/v6/jyh_4490_6_testbench.v +++ b/Quartus/v6/jyh_4490_6_testbench.v @@ -15,10 +15,10 @@ end always#10 clk=~clk; always begin + #1500000; in=0; repeat(5) begin - #10000000; in=1; #1000000; in=0; @@ -34,7 +34,7 @@ begin #1000000; end in=0; - #10000000; + #15000000; end jyh_4490_mstate M1( diff --git a/Quartus/v6/jyh_4490_6_testbench_top.v b/Quartus/v6/jyh_4490_6_testbench_top.v index 7209ac9..d6ccaf5 100644 --- a/Quartus/v6/jyh_4490_6_testbench_top.v +++ b/Quartus/v6/jyh_4490_6_testbench_top.v @@ -4,17 +4,14 @@ reg clk; wire [6:0] code; wire [7:0] seg; wire [19:0] cnt; -reg clr; reg in; reg en; wire subclk; wire [3:0] out0; -wire [3:0] out1; initial begin clk=0; in=0; - clr=1; en=1; end @@ -43,8 +40,8 @@ begin #15000000; end -jyh_4490_6_entry E1(.code(code),.seg(seg),.clk_50m(clk),.clr(clr),.en(en),.in(in), +jyh_4490_6_entry E1(.code(code),.seg(seg),.clk_50m(clk),.en(en),.in(in), //数码管型码 数码管位码 50M 清零信号 使能信号 按键 - .out0(out0),.out1(out1),.subclk(subclk)); + .out0(out0),.subclk(subclk)); //计数值 消抖值 endmodule \ No newline at end of file diff --git a/Quartus/v6_testbench/jyh_4490_6.cr.mti b/Quartus/v6_testbench/jyh_4490_6.cr.mti index db15be1..64aba45 100644 --- a/Quartus/v6_testbench/jyh_4490_6.cr.mti +++ b/Quartus/v6_testbench/jyh_4490_6.cr.mti @@ -1,11 +1,4 @@ -/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v -Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 --- Compiling module jyh_4490_6_testbench - -Top level modules: - jyh_4490_6_testbench - -} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v +/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module jyh_4490_mstate diff --git a/Quartus/v6_testbench/jyh_4490_6.mpf b/Quartus/v6_testbench/jyh_4490_6.mpf index aa66082..4340c2c 100644 --- a/Quartus/v6_testbench/jyh_4490_6.mpf +++ b/Quartus/v6_testbench/jyh_4490_6.mpf @@ -413,9 +413,9 @@ Project_DefaultLib = work Project_SortMethod = unused Project_Files_Count = 2 Project_File_0 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v -Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652112121 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652177049 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 Project_File_1 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v -Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1652112079 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1652112350 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 1 Project_Sim_0 = Simulation 1 Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_6_testbench folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {} diff --git a/Quartus/v6_testbench/transcript b/Quartus/v6_testbench/transcript index 7330dc2..808c0d2 100644 --- a/Quartus/v6_testbench/transcript +++ b/Quartus/v6_testbench/transcript @@ -1,92 +1,16 @@ # Compile of jyh_4490_6_testbench.v was successful. -# Compile of jyh_4490_mstate.v was successful. -# 2 compiles, 0 failed with no errors. -vsim work.jyh_4490_6_testbench -# vsim work.jyh_4490_6_testbench -# Start time: 23:55:10 on May 09,2022 -# Loading work.jyh_4490_6_testbench -# Loading work.jyh_4490_mstate -# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'. -# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39 -# Error loading design -# End time: 23:55:10 on May 09,2022, Elapsed time: 0:00:00 -# Errors: 1, Warnings: 7 -vsim work.jyh_4490_6_testbench -# vsim work.jyh_4490_6_testbench -# Start time: 23:55:11 on May 09,2022 -# Loading work.jyh_4490_6_testbench -# Loading work.jyh_4490_mstate -# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'. -# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39 -# Error loading design -# End time: 23:55:11 on May 09,2022, Elapsed time: 0:00:00 -# Errors: 1, Warnings: 1 -# can't read "Startup(-L)": no such element in array -# Load canceled -# Compile of jyh_4490_6_testbench.v failed with 1 errors. -# Compile of jyh_4490_6_testbench.v was successful. vsim work.jyh_4490_6_testbench # vsim work.jyh_4490_6_testbench -# Start time: 23:57:01 on May 09,2022 -# Loading work.jyh_4490_6_testbench -# Loading work.jyh_4490_mstate -add wave -position end sim:/jyh_4490_6_testbench/clk -add wave -position end sim:/jyh_4490_6_testbench/clr -add wave -position end sim:/jyh_4490_6_testbench/in -add wave -position end sim:/jyh_4490_6_testbench/out -add wave -position end sim:/jyh_4490_6_testbench/cnt -run -all -# Compile of jyh_4490_6_testbench.v was successful. -# Compile of jyh_4490_mstate.v was successful. -# 2 compiles, 0 failed with no errors. -vsim work.jyh_4490_6_testbench -# End time: 23:59:24 on May 09,2022, Elapsed time: 0:02:23 -# Errors: 0, Warnings: 4 -# vsim work.jyh_4490_6_testbench -# Start time: 23:59:24 on May 09,2022 -# Loading work.jyh_4490_6_testbench -# Loading work.jyh_4490_mstate -add wave -position end sim:/jyh_4490_6_testbench/clk -add wave -position end sim:/jyh_4490_6_testbench/in -add wave -position end sim:/jyh_4490_6_testbench/out -add wave -position end sim:/jyh_4490_6_testbench/cnt -run -all -# Compile of jyh_4490_6_testbench.v was successful. -# Compile of jyh_4490_mstate.v was successful. -# 2 compiles, 0 failed with no errors. -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# running -vsim work.jyh_4490_6_testbench -# End time: 00:03:02 on May 10,2022, Elapsed time: 0:03:38 -# Errors: 0, Warnings: 2 -# vsim work.jyh_4490_6_testbench -# Start time: 00:03:02 on May 10,2022 +# Start time: 18:05:59 on May 10,2022 # Loading work.jyh_4490_6_testbench # Loading work.jyh_4490_mstate # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'. Expected 5, found 4. -# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 38 -# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v(38): [TFMPC] - Missing connection for port 'en'. +# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 40 +# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v(40): [TFMPC] - Missing connection for port 'en'. add wave -position end sim:/jyh_4490_6_testbench/clk add wave -position end sim:/jyh_4490_6_testbench/in add wave -position end sim:/jyh_4490_6_testbench/en add wave -position end sim:/jyh_4490_6_testbench/out add wave -position end sim:/jyh_4490_6_testbench/cnt +run -continue run -all -# Break key hit -# Simulation stop requested. -# End time: 00:05:02 on May 10,2022, Elapsed time: 0:02:00 -# Errors: 0, Warnings: 4 diff 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