diff --git a/Quartus/Design/design.v b/Quartus/Design/design.v deleted file mode 100644 index fe779f2..0000000 --- a/Quartus/Design/design.v +++ /dev/null @@ -1,91 +0,0 @@ -module design( - input wire clk,//50MHz时钟 - output reg led, //用于指示 - input wire rst_n, - input wire rxd, - output wire txd, - inout dht_io -); - - reg [31:0]cnt; - reg led_f1,tx_flag; - always@(posedge clk) - begin - led_f1 <= led; - tx_flag <= led &(~led_f1); - if(cnt >= 32'd25000000 - 1) - begin - cnt <= 0; - led <=~led; - end - else begin - cnt <= cnt + 1'b1 ; - end - end - //-------------------------------------------- - localparam s_s1=0; - localparam s_s2=1; - localparam s_s3=2; - localparam s_s4=3; - reg [7:0]send_data; - reg to_uart_valid , to_uart_ready; - reg [2:0]send_st; - reg [7:0]data_cnt; - always@(posedge clk) - begin - if(!rst_n)begin - to_uart_ready <= 1'b0; - to_uart_valid <= 1'b0; - send_data <= 8'd0; - send_st<= s_s1; - data_cnt <= 8'd0; - end - - else begin - case(send_st) - s_s1:begin//待机 - if(tx_flag)begin - send_st <= s_s2; - to_uart_valid <= 1'b0; - to_uart_ready<= 1'b0; - data_cnt <= 8'd0; - send_data <= 9; - end - else begin - to_uart_valid <= 1'b0; - to_uart_ready<= 1'b0; - end - end - s_s2:begin - if(data_cnt <= 8'd8-1'b1)begin - to_uart_valid <= 1'b1; - send_data <= data_cnt+1; - data_cnt <= data_cnt + 1'b1; - send_st <= (data_cnt >= 8'd5-1)?s_s3:s_s2; - end - end - s_s3:begin - to_uart_valid <= 1'b0; - to_uart_ready <= 1'b1; - send_st <= s_s1; - data_cnt<=8'd0; - end - default :send_st <= s_s1; - endcase - end - end - -uart_screen u0 ( - .rs232_0_to_uart_data (send_data), // rs232_0_avalon_data_transmit_sink.data - .rs232_0_to_uart_error (), // .error - .rs232_0_to_uart_valid (to_uart_valid), // .valid - .rs232_0_to_uart_ready (to_uart_ready), // .ready - .rs232_0_UART_RXD (rxd), // rs232_0_external_interface.RXD - .rs232_0_UART_TXD (txd), // .TXD - .clk_clk (clk), // clk.clk - .reset_reset_n (rst_n) // reset.reset_n - ); - - - -endmodule \ No newline at end of file diff --git a/Quartus/Design/.qsys_edit/UART.xml b/Quartus/UART_Design/.qsys_edit/UART.xml similarity index 100% rename from Quartus/Design/.qsys_edit/UART.xml rename to Quartus/UART_Design/.qsys_edit/UART.xml diff --git a/Quartus/Design/.qsys_edit/UART_schematic.nlv b/Quartus/UART_Design/.qsys_edit/UART_schematic.nlv similarity index 100% rename from Quartus/Design/.qsys_edit/UART_schematic.nlv rename to Quartus/UART_Design/.qsys_edit/UART_schematic.nlv diff --git a/Quartus/Design/.qsys_edit/filters.xml b/Quartus/UART_Design/.qsys_edit/filters.xml similarity index 100% rename from Quartus/Design/.qsys_edit/filters.xml rename to Quartus/UART_Design/.qsys_edit/filters.xml diff --git a/Quartus/Design/.qsys_edit/preferences.xml b/Quartus/UART_Design/.qsys_edit/preferences.xml similarity index 100% rename from Quartus/Design/.qsys_edit/preferences.xml rename to Quartus/UART_Design/.qsys_edit/preferences.xml diff --git a/Quartus/Design/.qsys_edit/uart_screen.xml b/Quartus/UART_Design/.qsys_edit/uart_screen.xml similarity index 100% rename from Quartus/Design/.qsys_edit/uart_screen.xml rename to Quartus/UART_Design/.qsys_edit/uart_screen.xml diff --git a/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv b/Quartus/UART_Design/.qsys_edit/uart_screen_schematic.nlv similarity index 100% rename from Quartus/Design/.qsys_edit/uart_screen_schematic.nlv rename to Quartus/UART_Design/.qsys_edit/uart_screen_schematic.nlv diff --git a/Quartus/Design/UART.sopcinfo b/Quartus/UART_Design/UART.sopcinfo similarity index 100% rename from Quartus/Design/UART.sopcinfo rename to Quartus/UART_Design/UART.sopcinfo diff --git a/Quartus/Design/UART/UART.bsf b/Quartus/UART_Design/UART/UART.bsf similarity index 100% rename from Quartus/Design/UART/UART.bsf rename to Quartus/UART_Design/UART/UART.bsf diff --git a/Quartus/Design/UART/UART.cmp b/Quartus/UART_Design/UART/UART.cmp similarity index 100% rename from Quartus/Design/UART/UART.cmp rename to Quartus/UART_Design/UART/UART.cmp diff --git a/Quartus/Design/UART/UART.html b/Quartus/UART_Design/UART/UART.html similarity index 100% rename from Quartus/Design/UART/UART.html rename to Quartus/UART_Design/UART/UART.html diff --git a/Quartus/Design/UART/UART.xml b/Quartus/UART_Design/UART/UART.xml similarity index 100% rename from Quartus/Design/UART/UART.xml rename to Quartus/UART_Design/UART/UART.xml diff --git a/Quartus/Design/UART/UART_bb.v b/Quartus/UART_Design/UART/UART_bb.v similarity index 100% rename from Quartus/Design/UART/UART_bb.v rename to Quartus/UART_Design/UART/UART_bb.v diff --git a/Quartus/Design/UART/UART_generation.rpt b/Quartus/UART_Design/UART/UART_generation.rpt similarity index 100% rename from Quartus/Design/UART/UART_generation.rpt rename to Quartus/UART_Design/UART/UART_generation.rpt diff --git a/Quartus/Design/UART/UART_generation_previous.rpt b/Quartus/UART_Design/UART/UART_generation_previous.rpt similarity index 100% rename from Quartus/Design/UART/UART_generation_previous.rpt rename to Quartus/UART_Design/UART/UART_generation_previous.rpt diff --git a/Quartus/Design/UART/UART_inst.v b/Quartus/UART_Design/UART/UART_inst.v similarity index 100% rename from Quartus/Design/UART/UART_inst.v rename to Quartus/UART_Design/UART/UART_inst.v diff --git a/Quartus/Design/UART/synthesis/UART.debuginfo b/Quartus/UART_Design/UART/synthesis/UART.debuginfo similarity index 100% rename from Quartus/Design/UART/synthesis/UART.debuginfo rename to Quartus/UART_Design/UART/synthesis/UART.debuginfo diff --git a/Quartus/Design/UART/synthesis/UART.qip b/Quartus/UART_Design/UART/synthesis/UART.qip similarity index 100% rename from Quartus/Design/UART/synthesis/UART.qip rename to Quartus/UART_Design/UART/synthesis/UART.qip diff --git a/Quartus/Design/UART/synthesis/UART.v b/Quartus/UART_Design/UART/synthesis/UART.v similarity index 100% rename from Quartus/Design/UART/synthesis/UART.v rename to Quartus/UART_Design/UART/synthesis/UART.v diff --git a/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v b/Quartus/UART_Design/UART/synthesis/submodules/UART_rs232_0.v similarity index 100% rename from Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v rename to Quartus/UART_Design/UART/synthesis/submodules/UART_rs232_0.v diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v b/Quartus/UART_Design/UART/synthesis/submodules/altera_up_rs232_counters.v similarity index 100% rename from Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v rename to Quartus/UART_Design/UART/synthesis/submodules/altera_up_rs232_counters.v diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v b/Quartus/UART_Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v similarity index 100% rename from Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v rename to Quartus/UART_Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v b/Quartus/UART_Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v similarity index 100% rename from Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v rename to Quartus/UART_Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v b/Quartus/UART_Design/UART/synthesis/submodules/altera_up_sync_fifo.v similarity index 100% rename from Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v rename to Quartus/UART_Design/UART/synthesis/submodules/altera_up_sync_fifo.v diff --git a/Quartus/UART_Design/UART_design.v b/Quartus/UART_Design/UART_design.v new file mode 100644 index 0000000..6f9fb75 --- /dev/null +++ b/Quartus/UART_Design/UART_design.v @@ -0,0 +1,107 @@ +module UART_design( + input wire clk, //50MHz clock + output reg led, //led + input wire rst_n, //rst + input wire rxd, // UART RXD + output wire txd // UART TXD +); + + reg [31:0]cnt; //Clock Posedge Counter + reg led_f1,tx_flag; //Flags + localparam s_s1=0; //State Machine Param + localparam s_s2=1; + localparam s_s3=2; + localparam s_s4=3; + reg [7:0]data[64]; //UART Data to be send + reg [7:0]send_data; //UART Send Buffer + + //IP Core register + reg to_uart_valid , to_uart_ready; + reg [2:0]send_st; + reg [7:0]data_cnt; + + //Save Data + initial begin + data[0]=8'h67; data[1]=8'h30; data[2]=8'h2E; data[3]=8'h74; data[4]=8'h78; data[5]=8'h74; data[6]=8'h3D; data[7]=8'h22; + data[8]=8'hCF; data[9]=8'hB2; data[10]=8'hD3;data[11]=8'hAD; data[12]=8'hB6;data[13]=8'hFE;data[14]=8'hCA;data[15]=8'hAE; + data[16]=8'hB4;data[17]=8'hF3;data[18]=8'hA1;data[19]=8'hA2; data[20]=8'hD3;data[21]=8'hC0;data[22]=8'hD4;data[23]=8'hB6; + data[24]=8'hB8;data[25]=8'hFA;data[26]=8'hB5;data[27]=8'hB3; data[28]=8'hD7;data[29]=8'hDF;data[29]=8'hA1;data[31]=8'hA2; + data[32]=8'hB7;data[33]=8'hDC;data[34]=8'hBD;data[35]=8'hF8; data[36]=8'hD0;data[37]=8'hC2;data[38]=8'hD5;data[39]=8'hF7; + data[40]=8'hB3;data[41]=8'hCC;data[42]=8'hA1;data[43]=8'hA3; data[44]=8'h22;data[45]=8'hFF;data[46]=8'hFF;data[47]=8'hFF; + data[48]=8'h70;data[49]=8'h30;data[50]=8'h2E;data[51]=8'h70; data[52]=8'h69;data[53]=8'h63;data[54]=8'h3D;data[55]=8'h30; + data[56]=8'hFF;data[57]=8'hFF;data[58]=8'hFF;data[59]=8'h00; data[60]=8'h00;data[61]=8'h00;data[62]=8'h00;data[63]=8'h00; + + end + + always@(posedge clk) + begin + led_f1 <= led; + tx_flag <= led &(~led_f1); + if(cnt >= 32'd25000000 - 1) + begin + cnt <= 0; + led <=~led; + end + else begin + cnt <= cnt + 1'b1 ; + end + end + + always@(posedge clk) + begin + if(!rst_n)begin + to_uart_ready <= 1'b0; + to_uart_valid <= 1'b0; + send_data <= 8'd0; + send_st<= s_s1; + data_cnt <= 8'd0; + end + + else begin + case(send_st) + s_s1:begin //s1:idle + if(tx_flag)begin + send_st <= s_s2; + to_uart_valid <= 1'b0; + to_uart_ready<= 1'b0; + data_cnt <= 8'd0; + send_data <= 9; + end + else begin + to_uart_valid <= 1'b0; + to_uart_ready<= 1'b0; + end + end + s_s2:begin //s2:send + if(data_cnt <= 8'd64-1'b1)begin + to_uart_valid <= 1'b1; + send_data <= data[data_cnt]; + data_cnt <= data_cnt + 1'b1; + send_st <= (data_cnt >= 8'd64-1'b1)?s_s3:s_s2; + end + end + s_s3:begin //s2:send over + to_uart_valid <= 1'b0; + to_uart_ready <= 1'b1; + send_st <= s_s1; + data_cnt<=8'd0; + end + default :send_st <= s_s1; + endcase + end + end + +uart_screen u0 ( + .rs232_0_to_uart_data (send_data), // rs232_0_avalon_data_transmit_sink.data + .rs232_0_to_uart_error (), // .error + .rs232_0_to_uart_valid (to_uart_valid), // .valid + .rs232_0_to_uart_ready (to_uart_ready), // .ready + .rs232_0_UART_RXD (rxd), // rs232_0_external_interface.RXD + .rs232_0_UART_TXD (txd), // .TXD + .clk_clk (clk), // clk.clk + .reset_reset_n (rst_n) // reset.reset_n + ); + + + +endmodule \ No newline at end of file diff --git a/Quartus/Design/design.qpf b/Quartus/UART_Design/design.qpf similarity index 100% rename from Quartus/Design/design.qpf rename to Quartus/UART_Design/design.qpf diff --git a/Quartus/Design/design.qsf b/Quartus/UART_Design/design.qsf similarity index 84% rename from Quartus/Design/design.qsf rename to Quartus/UART_Design/design.qsf index 1ca0cab..d06678e 100644 --- a/Quartus/Design/design.qsf +++ b/Quartus/UART_Design/design.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE6E22C8 -set_global_assignment -name TOP_LEVEL_ENTITY design +set_global_assignment -name TOP_LEVEL_ENTITY UART_design set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:36:33 五月 24, 2022" set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" @@ -48,7 +48,11 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name QSYS_FILE uart_screen.qsys set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name VERILOG_FILE design.v \ No newline at end of file +set_global_assignment -name VERILOG_FILE UART_design.v +set_global_assignment -name QSYS_FILE uart_screen.qsys +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/Design/uart_screen.qsys b/Quartus/UART_Design/uart_screen.qsys similarity index 100% rename from Quartus/Design/uart_screen.qsys rename to Quartus/UART_Design/uart_screen.qsys diff --git a/Quartus/Design/uart_screen.sopcinfo b/Quartus/UART_Design/uart_screen.sopcinfo similarity index 99% rename from Quartus/Design/uart_screen.sopcinfo rename to Quartus/UART_Design/uart_screen.sopcinfo index 866f24c..26118ed 100644 --- a/Quartus/Design/uart_screen.sopcinfo +++ b/Quartus/UART_Design/uart_screen.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1655177123 + 1656147571 false true false diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc b/Quartus/UART_Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc rename to Quartus/UART_Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.v b/Quartus/UART_Design/uart_screen/synthesis/submodules/altera_reset_controller.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.v rename to Quartus/UART_Design/uart_screen/synthesis/submodules/altera_reset_controller.v diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v b/Quartus/UART_Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v rename to Quartus/UART_Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v b/Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v rename to Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v b/Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v rename to Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v b/Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v rename to Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v b/Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v rename to Quartus/UART_Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v diff --git a/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v b/Quartus/UART_Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v rename to Quartus/UART_Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo b/Quartus/UART_Design/uart_screen/synthesis/uart_screen.debuginfo similarity index 100% rename from Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo rename to Quartus/UART_Design/uart_screen/synthesis/uart_screen.debuginfo diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.qip b/Quartus/UART_Design/uart_screen/synthesis/uart_screen.qip similarity index 100% rename from Quartus/Design/uart_screen/synthesis/uart_screen.qip rename to Quartus/UART_Design/uart_screen/synthesis/uart_screen.qip diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.v b/Quartus/UART_Design/uart_screen/synthesis/uart_screen.v similarity index 100% rename from Quartus/Design/uart_screen/synthesis/uart_screen.v rename to Quartus/UART_Design/uart_screen/synthesis/uart_screen.v diff --git a/Quartus/Design/uart_screen/uart_screen.bsf b/Quartus/UART_Design/uart_screen/uart_screen.bsf similarity index 100% rename from Quartus/Design/uart_screen/uart_screen.bsf rename to Quartus/UART_Design/uart_screen/uart_screen.bsf diff --git a/Quartus/Design/uart_screen/uart_screen.cmp b/Quartus/UART_Design/uart_screen/uart_screen.cmp similarity index 100% rename from Quartus/Design/uart_screen/uart_screen.cmp rename to Quartus/UART_Design/uart_screen/uart_screen.cmp diff --git a/Quartus/Design/uart_screen/uart_screen.html b/Quartus/UART_Design/uart_screen/uart_screen.html similarity index 100% rename from Quartus/Design/uart_screen/uart_screen.html rename to Quartus/UART_Design/uart_screen/uart_screen.html diff --git a/Quartus/Design/uart_screen/uart_screen.ppf b/Quartus/UART_Design/uart_screen/uart_screen.ppf similarity index 100% rename from Quartus/Design/uart_screen/uart_screen.ppf rename to Quartus/UART_Design/uart_screen/uart_screen.ppf diff --git a/Quartus/Design/uart_screen/uart_screen.xml b/Quartus/UART_Design/uart_screen/uart_screen.xml similarity index 100% rename from Quartus/Design/uart_screen/uart_screen.xml rename to Quartus/UART_Design/uart_screen/uart_screen.xml diff --git a/Quartus/Design/uart_screen/uart_screen_bb.v b/Quartus/UART_Design/uart_screen/uart_screen_bb.v similarity index 100% rename from Quartus/Design/uart_screen/uart_screen_bb.v rename to Quartus/UART_Design/uart_screen/uart_screen_bb.v diff --git a/Quartus/Design/uart_screen/uart_screen_generation.rpt b/Quartus/UART_Design/uart_screen/uart_screen_generation.rpt similarity index 100% rename from Quartus/Design/uart_screen/uart_screen_generation.rpt rename to Quartus/UART_Design/uart_screen/uart_screen_generation.rpt diff --git a/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt b/Quartus/UART_Design/uart_screen/uart_screen_generation_previous.rpt similarity index 100% rename from Quartus/Design/uart_screen/uart_screen_generation_previous.rpt rename to Quartus/UART_Design/uart_screen/uart_screen_generation_previous.rpt diff --git a/Quartus/Design/uart_screen/uart_screen_inst.v b/Quartus/UART_Design/uart_screen/uart_screen_inst.v similarity index 100% rename from Quartus/Design/uart_screen/uart_screen_inst.v rename to Quartus/UART_Design/uart_screen/uart_screen_inst.v