diff --git a/Quartus/Design/.qsys_edit/preferences.xml b/Quartus/Design/.qsys_edit/preferences.xml index 7d2bdc4..cfba7a7 100644 --- a/Quartus/Design/.qsys_edit/preferences.xml +++ b/Quartus/Design/.qsys_edit/preferences.xml @@ -7,8 +7,7 @@ - - + + diff --git a/Quartus/Design/.qsys_edit/uart_screen.xml b/Quartus/Design/.qsys_edit/uart_screen.xml index 16f3996..00957b5 100644 --- a/Quartus/Design/.qsys_edit/uart_screen.xml +++ b/Quartus/Design/.qsys_edit/uart_screen.xml @@ -836,7 +836,7 @@ - + dock.single.Clock\ Domains\ \-\ Beta dock.single.IP\ Catalog @@ -939,7 +939,7 @@ - + dock.single.Messages dock.single.Generation\ Messages @@ -1005,10 +1005,10 @@ - - + + - Messages + IP Catalog @@ -1084,10 +1084,10 @@ - - + + - IP Catalog + Messages @@ -1095,7 +1095,7 @@ - 1 + 0 0 dock.PlaceholderList @@ -1348,12 +1348,9 @@ dock.single.Clock\ Domains\ \-\ Beta - - - - - - + + + @@ -1859,15 +1856,13 @@ dock.single.Clock\ Domains\ \-\ Beta - - - - - + + + - 1 + 2 dock.single.Clock\ Domains\ \-\ Beta diff --git a/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv b/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv index 8c3ff98..f809aa2 100644 --- a/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv +++ b/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv @@ -1,11 +1,14 @@ # # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35 # -preplace inst unsaved.rs232_0 -pg 1 -lvl 1 -y 30 -preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20 -preplace netloc EXPORTunsaved(SLAVE)unsaved.clk,(SLAVE)rs232_0.clk) 1 0 1 NJ -preplace netloc EXPORTunsaved(SLAVE)unsaved.interrupt,(SLAVE)rs232_0.interrupt) 1 0 1 NJ -preplace netloc EXPORTunsaved(SLAVE)unsaved.reset,(SLAVE)rs232_0.reset) 1 0 1 NJ -preplace netloc EXPORTunsaved(SLAVE)unsaved.avalon_rs232_slave,(SLAVE)rs232_0.avalon_rs232_slave) 1 0 1 NJ -preplace netloc EXPORTunsaved(SLAVE)unsaved.external_interface,(SLAVE)rs232_0.external_interface) 1 0 1 NJ -levelinfo -pg 1 0 120 320 -levelinfo -hier unsaved 130 160 310 +preplace inst uart_screen.clk_0 -pg 1 -lvl 1 -y 30 +preplace inst uart_screen.rs232_0 -pg 1 -lvl 2 -y 90 +preplace inst uart_screen -pg 1 -lvl 1 -y 40 -regy -20 +preplace netloc EXPORTuart_screen(SLAVE)uart_screen.rs232_0_avalon_data_transmit_sink,(SLAVE)rs232_0.avalon_data_transmit_sink) 1 0 2 NJ 100 NJ +preplace netloc EXPORTuart_screen(SLAVE)uart_screen.clk,(SLAVE)clk_0.clk_in) 1 0 1 NJ +preplace netloc EXPORTuart_screen(MASTER)rs232_0.avalon_data_receive_source,(MASTER)uart_screen.rs232_0_avalon_data_receive_source) 1 2 1 N +preplace netloc EXPORTuart_screen(SLAVE)clk_0.clk_in_reset,(SLAVE)uart_screen.reset) 1 0 1 NJ +preplace netloc POINT_TO_POINTuart_screen(SLAVE)rs232_0.reset,(MASTER)clk_0.clk_reset) 1 1 1 410 +preplace netloc POINT_TO_POINTuart_screen(SLAVE)rs232_0.clk,(MASTER)clk_0.clk) 1 1 1 430 +preplace netloc EXPORTuart_screen(SLAVE)rs232_0.external_interface,(SLAVE)uart_screen.rs232_0_external_interface) 1 0 2 NJ 140 NJ +levelinfo -pg 1 0 200 900 +levelinfo -hier uart_screen 210 240 460 680 diff --git a/Quartus/Design/design.v b/Quartus/Design/design.v index bf9e4c8..fe779f2 100644 --- a/Quartus/Design/design.v +++ b/Quartus/Design/design.v @@ -1,14 +1,91 @@ +module design( + input wire clk,//50MHz时钟 + output reg led, //用于指示 + input wire rst_n, + input wire rxd, + output wire txd, + inout dht_io +); + + reg [31:0]cnt; + reg led_f1,tx_flag; + always@(posedge clk) + begin + led_f1 <= led; + tx_flag <= led &(~led_f1); + if(cnt >= 32'd25000000 - 1) + begin + cnt <= 0; + led <=~led; + end + else begin + cnt <= cnt + 1'b1 ; + end + end + //-------------------------------------------- + localparam s_s1=0; + localparam s_s2=1; + localparam s_s3=2; + localparam s_s4=3; + reg [7:0]send_data; + reg to_uart_valid , to_uart_ready; + reg [2:0]send_st; + reg [7:0]data_cnt; + always@(posedge clk) + begin + if(!rst_n)begin + to_uart_ready <= 1'b0; + to_uart_valid <= 1'b0; + send_data <= 8'd0; + send_st<= s_s1; + data_cnt <= 8'd0; + end + + else begin + case(send_st) + s_s1:begin//待机 + if(tx_flag)begin + send_st <= s_s2; + to_uart_valid <= 1'b0; + to_uart_ready<= 1'b0; + data_cnt <= 8'd0; + send_data <= 9; + end + else begin + to_uart_valid <= 1'b0; + to_uart_ready<= 1'b0; + end + end + s_s2:begin + if(data_cnt <= 8'd8-1'b1)begin + to_uart_valid <= 1'b1; + send_data <= data_cnt+1; + data_cnt <= data_cnt + 1'b1; + send_st <= (data_cnt >= 8'd5-1)?s_s3:s_s2; + end + end + s_s3:begin + to_uart_valid <= 1'b0; + to_uart_ready <= 1'b1; + send_st <= s_s1; + data_cnt<=8'd0; + end + default :send_st <= s_s1; + endcase + end + end + uart_screen u0 ( - .clk_clk (), // clk.clk - .reset_reset_n (), // reset.reset_n - .rs232_0_from_uart_ready (), // rs232_0_avalon_data_receive_source.ready - .rs232_0_from_uart_data (), // .data - .rs232_0_from_uart_error (), // .error - .rs232_0_from_uart_valid (), // .valid - .rs232_0_to_uart_data (), // rs232_0_avalon_data_transmit_sink.data - .rs232_0_to_uart_error (), // .error - .rs232_0_to_uart_valid (), // .valid - .rs232_0_to_uart_ready (), // .ready - .rs232_0_UART_RXD (), // rs232_0_external_interface.RXD - .rs232_0_UART_TXD () // .TXD + .rs232_0_to_uart_data (send_data), // rs232_0_avalon_data_transmit_sink.data + .rs232_0_to_uart_error (), // .error + .rs232_0_to_uart_valid (to_uart_valid), // .valid + .rs232_0_to_uart_ready (to_uart_ready), // .ready + .rs232_0_UART_RXD (rxd), // rs232_0_external_interface.RXD + .rs232_0_UART_TXD (txd), // .TXD + .clk_clk (clk), // clk.clk + .reset_reset_n (rst_n) // reset.reset_n ); + + + +endmodule \ No newline at end of file diff --git a/Quartus/Design/uart_screen.qsys b/Quartus/Design/uart_screen.qsys index d333fb3..83de5de 100644 --- a/Quartus/Design/uart_screen.qsys +++ b/Quartus/Design/uart_screen.qsys @@ -6,7 +6,7 @@ version="1.0" description="" tags="INTERNAL_COMPONENT=true" - categories="" /> + categories="System" /> - + @@ -93,7 +93,7 @@ - + diff --git a/Quartus/Design/uart_screen.sopcinfo b/Quartus/Design/uart_screen.sopcinfo index 8e54700..866f24c 100644 --- a/Quartus/Design/uart_screen.sopcinfo +++ b/Quartus/Design/uart_screen.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1653392990 + 1655177123 false true false @@ -424,7 +424,7 @@ the requested settings for a module instance. --> int - 115200 + 9600 false true true diff --git a/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v b/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v index 702bbdf..6af907e 100644 --- a/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v +++ b/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v @@ -55,9 +55,9 @@ module uart_screen_rs232_0 ( * Parameter Declarations * *****************************************************************************/ -parameter CW = 9; // Baud counter width -parameter BAUD_TICK_COUNT = 434; -parameter HALF_BAUD_TICK_COUNT = 217; +parameter CW = 13; // Baud counter width +parameter BAUD_TICK_COUNT = 5208; +parameter HALF_BAUD_TICK_COUNT = 2604; parameter TDW = 10; // Total data width parameter DW = 8; // Data width diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo b/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo index 51c0b8b..6d395be 100644 --- a/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo +++ b/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo @@ -1,7 +1,7 @@ - + com.altera.sopcmodel.ensemble.EClockAdapter @@ -53,7 +53,7 @@ int - 1653392990 + 1655177123 false true true @@ -101,7 +101,7 @@ java.lang.String - + design.qpf false true false @@ -482,7 +482,7 @@ the requested settings for a module instance. --> int - 115200 + 9600 false true true @@ -1610,5 +1610,5 @@ parameters are a RESULT of the module parameters. --> 21.1 21.1 842 - CCD9AC02D57D00000180F5E6E111 + 2C16DBA514B800000181603E9758 diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.qip b/Quartus/Design/uart_screen/synthesis/uart_screen.qip index 0b6225e..9f1c4c8 100644 --- a/Quartus/Design/uart_screen/synthesis/uart_screen.qip +++ b/Quartus/Design/uart_screen/synthesis/uart_screen.qip @@ -2,7 +2,7 @@ set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_VERSION "21.1" set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_ENV "Qsys" set_global_assignment -library "uart_screen" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../uart_screen.sopcinfo"] -set_global_assignment -entity "uart_screen" -library "uart_screen" -name SLD_INFO "QSYS_NAME uart_screen HAS_SOPCINFO 1 GENERATION_ID 1653392990" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name SLD_INFO "QSYS_NAME uart_screen HAS_SOPCINFO 1 GENERATION_ID 1655177123" set_global_assignment -library "uart_screen" -name MISC_FILE [file join $::quartus(qip_path) "../uart_screen.cmp"] set_global_assignment -library "uart_screen" -name SLD_FILE [file join $::quartus(qip_path) "uart_screen.debuginfo"] set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" @@ -15,7 +15,7 @@ set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMP set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "On" set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off" set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_VERSION "MS4w" -set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1MzM5Mjk5MA==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1NTE3NzEyMw==::QXV0byBHRU5FUkFUSU9OX0lE" set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0U2RTIyQzg=::QXV0byBERVZJQ0U=" set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" @@ -62,7 +62,7 @@ set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_VERSION "MTcuMQ==" set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_DESCRIPTION "UlMyMzIgVUFSVCBDb250cm9sbGVy" set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YXZhbG9uX2J1c190eXBl::U3RyZWFtaW5n::QXZhbG9uIFR5cGU=" -set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YmF1ZA==::MTE1MjAw::QmF1ZCBSYXRlIChicHMp" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YmF1ZA==::OTYwMA==::QmF1ZCBSYXRlIChicHMp" set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "cGFyaXR5::Tm9uZQ==::UGFyaXR5" set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "ZGF0YV9iaXRz::OA==::RGF0YSBCaXRz" set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "c3RvcF9iaXRz::MQ==::U3RvcCBCaXRz" diff --git a/Quartus/Design/uart_screen/uart_screen.html b/Quartus/Design/uart_screen/uart_screen.html index eef457d..5bf6de2 100644 --- a/Quartus/Design/uart_screen/uart_screen.html +++ b/Quartus/Design/uart_screen/uart_screen.html @@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
2022.05.24.19:49:502022.06.14.11:25:23 Datasheet
@@ -185,7 +185,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord baud - 115200 + 9600 parity @@ -229,7 +229,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord - +
generation took 0.00 secondsrendering took 0.03 secondsrendering took 0.01 seconds
diff --git a/Quartus/Design/uart_screen/uart_screen.xml b/Quartus/Design/uart_screen/uart_screen.xml index f15ee80..78e60b6 100644 --- a/Quartus/Design/uart_screen/uart_screen.xml +++ b/Quartus/Design/uart_screen/uart_screen.xml @@ -1,6 +1,6 @@ - + @@ -226,12 +226,12 @@ - + diff --git a/Quartus/Design/uart_screen/uart_screen_bb.v b/Quartus/Design/uart_screen/uart_screen_bb.v index 5adf74c..c6ef41a 100644 --- a/Quartus/Design/uart_screen/uart_screen_bb.v +++ b/Quartus/Design/uart_screen/uart_screen_bb.v @@ -1,7 +1,7 @@ module uart_screen ( - rs232_0_UART_RXD, - rs232_0_UART_TXD, + clk_clk, + reset_reset_n, rs232_0_from_uart_ready, rs232_0_from_uart_data, rs232_0_from_uart_error, @@ -10,11 +10,11 @@ module uart_screen ( rs232_0_to_uart_error, rs232_0_to_uart_valid, rs232_0_to_uart_ready, - clk_clk, - reset_reset_n); + rs232_0_UART_RXD, + rs232_0_UART_TXD); - input rs232_0_UART_RXD; - output rs232_0_UART_TXD; + input clk_clk; + input reset_reset_n; input rs232_0_from_uart_ready; output [7:0] rs232_0_from_uart_data; output rs232_0_from_uart_error; @@ -23,6 +23,6 @@ module uart_screen ( input rs232_0_to_uart_error; input rs232_0_to_uart_valid; output rs232_0_to_uart_ready; - input clk_clk; - input reset_reset_n; + input rs232_0_UART_RXD; + output rs232_0_UART_TXD; endmodule diff --git a/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt b/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt index 27df025..943e128 100644 --- a/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt +++ b/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt @@ -2,6 +2,8 @@ Info: Starting: Create block symbol file (.bsf) Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen --family="Cyclone IV E" --part=EP4CE6E22C8 Progress: Loading Design/uart_screen.qsys Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] Progress: Parameterizing module rs232_0 Progress: Building connections @@ -15,6 +17,8 @@ Info: Starting: Create HDL design files for synthesis Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8 Progress: Loading Design/uart_screen.qsys Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] Progress: Parameterizing module rs232_0 Progress: Building connections @@ -23,8 +27,8 @@ Progress: Validating Progress: Done reading input file Info: uart_screen: Generating uart_screen "uart_screen" for QUARTUS_SYNTH Info: rs232_0: Starting Generation of RS232 UART -Error: rs232_0: The input clock frequency must be known at generation time. Info: rs232_0: "uart_screen" instantiated altera_up_avalon_rs232 "rs232_0" -Info: uart_screen: Done "uart_screen" with 2 modules, 6 files -Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings +Info: rst_controller: "uart_screen" instantiated altera_reset_controller "rst_controller" +Info: uart_screen: Done "uart_screen" with 3 modules, 9 files +Info: qsys-generate succeeded. Info: Finished: Create HDL design files for synthesis diff --git a/Quartus/Design/uart_screen/uart_screen_inst.v b/Quartus/Design/uart_screen/uart_screen_inst.v index 3aa6c7c..63abf47 100644 --- a/Quartus/Design/uart_screen/uart_screen_inst.v +++ b/Quartus/Design/uart_screen/uart_screen_inst.v @@ -1,6 +1,6 @@ uart_screen u0 ( - .rs232_0_UART_RXD (), // rs232_0_external_interface.RXD - .rs232_0_UART_TXD (), // .TXD + .clk_clk (), // clk.clk + .reset_reset_n (), // reset.reset_n .rs232_0_from_uart_ready (), // rs232_0_avalon_data_receive_source.ready .rs232_0_from_uart_data (), // .data .rs232_0_from_uart_error (), // .error @@ -9,7 +9,7 @@ .rs232_0_to_uart_error (), // .error .rs232_0_to_uart_valid (), // .valid .rs232_0_to_uart_ready (), // .ready - .clk_clk (), // clk.clk - .reset_reset_n () // reset.reset_n + .rs232_0_UART_RXD (), // rs232_0_external_interface.RXD + .rs232_0_UART_TXD () // .TXD );