Merge commit 'b95c2067d63dcd1868b2c54fa2bdc7db23fdbc24'
This commit is contained in:
iridiumR
commit
61cc77b855
7 changed files with 1546 additions and 73 deletions
1357
Quartus/v4/Waveform.vwf
Normal file
1357
Quartus/v4/Waveform.vwf
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File diff suppressed because it is too large
Load diff
61
Quartus/v4/greybox_tmp/cbx_args.txt
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61
Quartus/v4/greybox_tmp/cbx_args.txt
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@ -0,0 +1,61 @@
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BANDWIDTH_TYPE=AUTO
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CLK0_DIVIDE_BY=1
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CLK0_DUTY_CYCLE=50
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CLK0_MULTIPLY_BY=1
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CLK0_PHASE_SHIFT=0
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COMPENSATE_CLOCK=CLK0
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INCLK0_INPUT_FREQUENCY=166666
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INTENDED_DEVICE_FAMILY="Cyclone IV E"
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LPM_TYPE=altpll
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OPERATION_MODE=NORMAL
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PLL_TYPE=AUTO
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PORT_ACTIVECLOCK=PORT_UNUSED
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PORT_ARESET=PORT_USED
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PORT_CLKBAD0=PORT_UNUSED
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PORT_CLKBAD1=PORT_UNUSED
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PORT_CLKLOSS=PORT_UNUSED
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PORT_CLKSWITCH=PORT_UNUSED
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PORT_CONFIGUPDATE=PORT_UNUSED
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PORT_FBIN=PORT_UNUSED
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PORT_INCLK0=PORT_USED
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PORT_INCLK1=PORT_UNUSED
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PORT_LOCKED=PORT_USED
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PORT_PFDENA=PORT_UNUSED
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PORT_PHASECOUNTERSELECT=PORT_UNUSED
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PORT_PHASEDONE=PORT_UNUSED
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PORT_PHASESTEP=PORT_UNUSED
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PORT_PHASEUPDOWN=PORT_UNUSED
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PORT_PLLENA=PORT_UNUSED
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PORT_SCANACLR=PORT_UNUSED
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PORT_SCANCLK=PORT_UNUSED
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PORT_SCANCLKENA=PORT_UNUSED
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PORT_SCANDATA=PORT_UNUSED
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PORT_SCANDATAOUT=PORT_UNUSED
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PORT_SCANDONE=PORT_UNUSED
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PORT_SCANREAD=PORT_UNUSED
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PORT_SCANWRITE=PORT_UNUSED
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PORT_clk0=PORT_USED
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PORT_clk1=PORT_UNUSED
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PORT_clk2=PORT_UNUSED
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PORT_clk3=PORT_UNUSED
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PORT_clk4=PORT_UNUSED
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PORT_clk5=PORT_UNUSED
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PORT_clkena0=PORT_UNUSED
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PORT_clkena1=PORT_UNUSED
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PORT_clkena2=PORT_UNUSED
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PORT_clkena3=PORT_UNUSED
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PORT_clkena4=PORT_UNUSED
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PORT_clkena5=PORT_UNUSED
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PORT_extclk0=PORT_UNUSED
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PORT_extclk1=PORT_UNUSED
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PORT_extclk2=PORT_UNUSED
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PORT_extclk3=PORT_UNUSED
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SELF_RESET_ON_LOSS_LOCK=OFF
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WIDTH_CLOCK=5
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DEVICE_FAMILY="Cyclone IV E"
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CBX_AUTO_BLACKBOX=ALL
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areset
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inclk
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inclk
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clk
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locked
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@ -55,4 +55,40 @@ set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VERILOG_FILE jyh_4490_4_divider.v
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_location_assignment PIN_43 -to CO
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set_location_assignment PIN_89 -to clk
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set_location_assignment PIN_24 -to clr
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set_location_assignment PIN_103 -to code[0]
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set_location_assignment PIN_110 -to code[1]
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set_location_assignment PIN_106 -to code[2]
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set_location_assignment PIN_111 -to code[3]
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set_location_assignment PIN_104 -to code[4]
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set_location_assignment PIN_100 -to code[5]
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set_location_assignment PIN_112 -to code[6]
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set_location_assignment PIN_31 -to en
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set_location_assignment PIN_32 -to in0[0]
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set_location_assignment PIN_42 -to in0[1]
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set_location_assignment PIN_39 -to in0[2]
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set_location_assignment PIN_44 -to in0[3]
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set_location_assignment PIN_33 -to load
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set_location_assignment PIN_46 -to out0[0]
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set_location_assignment PIN_50 -to out0[1]
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set_location_assignment PIN_52 -to out0[2]
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set_location_assignment PIN_54 -to out0[3]
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set_location_assignment PIN_58 -to out1[0]
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set_location_assignment PIN_53 -to out1[1]
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set_location_assignment PIN_51 -to out1[2]
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set_location_assignment PIN_49 -to out1[3]
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set_location_assignment PIN_119 -to seg[0]
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set_location_assignment PIN_126 -to seg[1]
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set_location_assignment PIN_115 -to seg[2]
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set_location_assignment PIN_125 -to seg[3]
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set_location_assignment PIN_114 -to seg[4]
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set_location_assignment PIN_121 -to seg[5]
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set_location_assignment PIN_113 -to seg[6]
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set_location_assignment PIN_120 -to seg[7]
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set_location_assignment PIN_30 -to upd
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set_location_assignment PIN_90 -to clk_50m
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -20,42 +20,46 @@ begin
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if(load)
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begin
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Q<=in;
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end
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else if(co_flag)
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begin
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co<=1;
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co_flag=0;
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end
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else if(!co_flag)
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co<=0;
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//正反计数
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if(upd)
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begin
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if(Q>=4'd9)
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begin
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Q<=4'd0;
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co_flag=1;
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end
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else
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begin
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Q <= Q+1;
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end
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end
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else
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else
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begin
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if(co_flag)
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begin
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if(Q<=4'd0)
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begin
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Q<=4'd9;
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end
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else if(Q==4'd1)
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begin
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Q <= Q-1;
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co_flag=1;
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end
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else
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begin
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Q <= Q-1;
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end
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co<=1;
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co_flag=0;
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end
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else if(!co_flag)
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co<=0;
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//正反计数
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if(upd)
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begin
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if(Q>=4'd9)
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begin
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Q<=4'd0;
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co_flag=1;
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end
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else
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begin
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Q <= Q+1;
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end
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end
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else
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begin
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if(Q<=4'd0)
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begin
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Q<=4'd9;
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end
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else if(Q==4'd1)
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begin
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Q <= Q-1;
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co_flag=1;
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end
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else
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begin
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Q <= Q-1;
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end
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end
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end
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end
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else
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19
Quartus/v4/jyh_4490_4_divider.v
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19
Quartus/v4/jyh_4490_4_divider.v
Normal file
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@ -0,0 +1,19 @@
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module jyh_4490_4_divider(clk,clk_out);
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input clk;
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output reg clk_out;
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// localparam TARGET=100000;
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localparam TARGET=1;
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reg [19:0]counter=0;
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initial begin
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clk_out=0;
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end
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always @(posedge clk)
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begin
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counter=counter+1;
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if(counter==TARGET)
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begin
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counter=0;
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clk_out=!clk_out;
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end
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end
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endmodule
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@ -1,17 +1,17 @@
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//七段四位译码器
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module jyh_4490_4_encoder(sel,codeout,clk, d1, d2);
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module jyh_4490_4_encoder(sel,codeout,clk, d1, d2, d3, d4);
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input clk;
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input [6:0] d1, d2;
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output reg [1:0] sel; //位选
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input [6:0] d1, d2, d3, d4;
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output reg [3:0] sel; //位选
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output reg [6:0] codeout; //型码
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//当前位置数字
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reg [6:0] code_loc=2'b01;
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reg [6:0] code_loc;
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//实验性消影
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reg isEnable;
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reg [1:0] loc;
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reg [3:0] loc=4'b1000;
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//循环移位
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always @(posedge clk)
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@ -21,10 +21,14 @@ begin
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else
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begin
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isEnable<=1;
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if(loc==2'b01)
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loc=2'b10;
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else
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loc=2'b01;
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if(loc==4'b0001)
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loc=4'b10;
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else if(loc==4'b0010)
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loc=4'b100;
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else if(loc==4'b0100)
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loc=4'b1000;
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else if(loc==4'b1000)
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loc=4'b1;
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end
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end
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@ -33,8 +37,10 @@ begin
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if(isEnable)
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begin
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case (loc)
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2'b01: begin code_loc = d1; sel = 4'b10; end
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2'b10: begin code_loc = d2; sel = 4'b01; end
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4'b0001: begin code_loc = d1; sel = 4'b0001; end
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4'b0010: begin code_loc = d2; sel = 4'b0010; end
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4'b0100: begin code_loc = d3; sel = 4'b0100; end
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4'b1000: begin code_loc = d4; sel = 4'b1000; end
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endcase
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end
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end
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@ -1,27 +1,27 @@
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module jyh_4490_4_entry(out1, out0, code, sel, CO,
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module jyh_4490_4_entry(out1, out0, code, seg, CO,
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// 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
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in1, in0, load, clk, clr, en, upd);
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// 十位装载 个位装载 装载信号 计数时钟信号 清零信号 使能信号 正反计数标志位
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in1, in0, load, clk, clk_50m, subclk, clr, en, upd);
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// 十位装载 个位装载 装载信号 计数时钟信号 50M 分频信号 清零信号 使能信号 正反计数标志位
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output [3:0] out1;
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output [3:0] out0;
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output [6:0] code;
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output [7:0] sel;
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output [7:0] seg;
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output CO;
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input [3:0] in1;
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input [3:0] in0;
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input clk,load,clr,en,upd;
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input clk,load,clr,en,upd,clk_50m;
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//wire subclk;
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//jyh_4490_3_divide(
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//.clkin(clk),
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//.clkout(subclk)
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//);
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//分频器
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output subclk;
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jyh_4490_4_divider D1(
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.clk(clk_50m),
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.clk_out(subclk)
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);
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//个位计数器
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jyh_4490_4_counter c0(
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jyh_4490_4_counter C1(
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.Q(out0),
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.clk(clk),
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.co(CO),
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@ -32,31 +32,21 @@ jyh_4490_4_counter c0(
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.upd(upd));
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//十位计数器
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jyh_4490_4_counter c1(
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jyh_4490_4_counter C2(
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.Q(out1),
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.clk(CO||load),
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.clk(CO||(load && clk)),
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.clr(clr),
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.load(load),
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.in(in1),
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.load(load),
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.en(en),
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.upd(upd));
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//四位数码管译码器
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//jyh_4490_3_encoder e1(
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//.codeout(code),
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//.d1(out0),
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//.d2(out1),
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//.clk(clk),
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//.sel(sel[1:0])
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//);
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jyh_4490_4_simpleEncoder e1(
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jyh_4490_4_encoder E1(
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.codeout(code),
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.d1(out0),
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.clk(clk),
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.sel(sel[0:0])
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.d2(out1),
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.clk(subclk),
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.sel(seg[3:0])
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);
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endmodule
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