Merge commit 'b95c2067d63dcd1868b2c54fa2bdc7db23fdbc24'

Quartus/v4/greybox_tmp/cbx_args.txt

@@ -0,0 +1,61 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=1
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=1
+CLK0_PHASE_SHIFT=0
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=166666
+INTENDED_DEVICE_FAMILY="Cyclone IV E"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_USED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_USED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_UNUSED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+SELF_RESET_ON_LOSS_LOCK=OFF
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone IV E"
+CBX_AUTO_BLACKBOX=ALL
+areset
+inclk
+inclk
+clk
+locked

Quartus/v4/jyh_4490_4.qsf

@@ -55,4 +55,40 @@ set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name VERILOG_FILE jyh_4490_4_divider.v
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
+set_location_assignment PIN_43 -to CO
+set_location_assignment PIN_89 -to clk
+set_location_assignment PIN_24 -to clr
+set_location_assignment PIN_103 -to code[0]
+set_location_assignment PIN_110 -to code[1]
+set_location_assignment PIN_106 -to code[2]
+set_location_assignment PIN_111 -to code[3]
+set_location_assignment PIN_104 -to code[4]
+set_location_assignment PIN_100 -to code[5]
+set_location_assignment PIN_112 -to code[6]
+set_location_assignment PIN_31 -to en
+set_location_assignment PIN_32 -to in0[0]
+set_location_assignment PIN_42 -to in0[1]
+set_location_assignment PIN_39 -to in0[2]
+set_location_assignment PIN_44 -to in0[3]
+set_location_assignment PIN_33 -to load
+set_location_assignment PIN_46 -to out0[0]
+set_location_assignment PIN_50 -to out0[1]
+set_location_assignment PIN_52 -to out0[2]
+set_location_assignment PIN_54 -to out0[3]
+set_location_assignment PIN_58 -to out1[0]
+set_location_assignment PIN_53 -to out1[1]
+set_location_assignment PIN_51 -to out1[2]
+set_location_assignment PIN_49 -to out1[3]
+set_location_assignment PIN_119 -to seg[0]
+set_location_assignment PIN_126 -to seg[1]
+set_location_assignment PIN_115 -to seg[2]
+set_location_assignment PIN_125 -to seg[3]
+set_location_assignment PIN_114 -to seg[4]
+set_location_assignment PIN_121 -to seg[5]
+set_location_assignment PIN_113 -to seg[6]
+set_location_assignment PIN_120 -to seg[7]
+set_location_assignment PIN_30 -to upd
+set_location_assignment PIN_90 -to clk_50m
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Quartus/v4/jyh_4490_4_counter.v

@@ -20,8 +20,11 @@ begin
 		if(load)
 			begin
 			Q<=in;
+			co<=0;
 			end
-		else if(co_flag)
+		else
+		begin
+			if(co_flag)
 			begin
 				co<=1;
 				co_flag=0;
@@ -58,6 +61,7 @@ begin
 						end
 				end
 			end
+	end
 	else
 		Q<=0;
 end

Quartus/v4/jyh_4490_4_divider.v

@@ -0,0 +1,19 @@
+module jyh_4490_4_divider(clk,clk_out);
+	 input clk;
+	 output reg clk_out;
+//    localparam TARGET=100000;
+	localparam TARGET=1;
+    reg [19:0]counter=0; 
+    initial begin
+        clk_out=0;
+    end
+    always @(posedge clk)
+	 begin
+        counter=counter+1;
+        if(counter==TARGET)
+			begin
+            counter=0;
+            clk_out=!clk_out;
+        end
+    end
+endmodule

Quartus/v4/jyh_4490_4_encoder.v

@@ -1,17 +1,17 @@
 //七段四位译码器
-module jyh_4490_4_encoder(sel,codeout,clk, d1, d2);
+module jyh_4490_4_encoder(sel,codeout,clk, d1, d2, d3, d4);
 input clk;
-input [6:0] d1, d2;
+input [6:0] d1, d2, d3, d4;
-output reg [1:0] sel; //位选
+output reg [3:0] sel; //位选
 output reg [6:0] codeout; //型码
 
 
 //当前位置数字
-reg [6:0] code_loc=2'b01;
+reg [6:0] code_loc;
 
 //实验性消影
 reg isEnable;
-reg [1:0] loc;
+reg [3:0] loc=4'b1000;
 
 //循环移位
 always @(posedge clk)
@@ -21,10 +21,14 @@ begin
 	else
 		begin
 		isEnable<=1;
-		if(loc==2'b01)
+		if(loc==4'b0001)
-		loc=2'b10;
+		loc=4'b10;
-		else
+		else if(loc==4'b0010)
-		loc=2'b01;
+		loc=4'b100;
+		else if(loc==4'b0100)
+		loc=4'b1000;
+		else if(loc==4'b1000)
+		loc=4'b1;
 		end
 end
 
@@ -33,8 +37,10 @@ begin
 	if(isEnable)
 	begin
 	case (loc)
-		2'b01: begin code_loc = d1; sel = 4'b10; end
+		4'b0001: begin code_loc = d1; sel = 4'b0001; end
-		2'b10: begin code_loc = d2; sel = 4'b01; end
+		4'b0010: begin code_loc = d2; sel = 4'b0010; end
+		4'b0100: begin code_loc = d3; sel = 4'b0100; end
+		4'b1000: begin code_loc = d4; sel = 4'b1000; end
 	endcase
 	end
 end

Quartus/v4/jyh_4490_4_entry.v

@@ -1,27 +1,27 @@
-module jyh_4490_4_entry(out1,		out0,		code,			sel, 			CO,
+module jyh_4490_4_entry(out1,		out0,		code,			seg, 			CO,
 							//	十位输出 	个位输出 	数码管型码 	数码管位码 	进/借位标志位
-								in1,		in0,		load,		clk,			clr,			en,			upd);
+								in1,		in0,		load,		clk,			clk_50m,		subclk, 		clr,			en,			upd);
-							// 十位装载 	个位装载 	装载信号 	计数时钟信号  清零信号 		使能信号 		正反计数标志位
+							// 十位装载 	个位装载 	装载信号 	计数时钟信号  50M			分频信号		清零信号 		使能信号 		正反计数标志位
 
 output [3:0] out1;
 output [3:0] out0;
 output [6:0] code;
-output [7:0] sel;
+output [7:0] seg;
 output CO;
 input [3:0] in1;
 input [3:0] in0;
-input clk,load,clr,en,upd;
+input clk,load,clr,en,upd,clk_50m;
 
-
+//分频器
-//wire subclk;
+output subclk;
-//jyh_4490_3_divide(
+jyh_4490_4_divider D1(
-//.clkin(clk),
+.clk(clk_50m),
-//.clkout(subclk)
+.clk_out(subclk)
-//);
+);
 
 
 //个位计数器
-jyh_4490_4_counter c0(
+jyh_4490_4_counter C1(
 .Q(out0),
 .clk(clk),
 .co(CO),
@@ -32,31 +32,21 @@ jyh_4490_4_counter c0(
 .upd(upd));
 
 //十位计数器
-jyh_4490_4_counter c1(
+jyh_4490_4_counter C2(
 .Q(out1),
-.clk(CO||load),
+.clk(CO||(load && clk)),
 .clr(clr),
-.load(load),
 .in(in1),
+.load(load),
 .en(en),
 .upd(upd));
 
-
-
 //四位数码管译码器
-//jyh_4490_3_encoder e1(
+jyh_4490_4_encoder E1(
-//.codeout(code),
-//.d1(out0),
-//.d2(out1),
-//.clk(clk),
-//.sel(sel[1:0])
-//);
-
-jyh_4490_4_simpleEncoder e1(
 .codeout(code),
 .d1(out0),
-.clk(clk),
+.d2(out1),
-.sel(sel[0:0])
+.clk(subclk),
+.sel(seg[3:0])
 );
-
 endmodule