diff --git a/Quartus/Design/.qsys_edit/UART.xml b/Quartus/Design/.qsys_edit/UART.xml new file mode 100644 index 0000000..e3e118f --- /dev/null +++ b/Quartus/Design/.qsys_edit/UART.xml @@ -0,0 +1,2260 @@ + + + + eclipse + + + + + + + + + + + + ccontrol north + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + external + true + + + 0 + dock.PlaceholderList + + + + + + + dock.CExternalizeArea + + + + + + + + + ccontrol south + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol east + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol center + true + + false + + + + + + + + + + + + + + + + + + + + + + + + + dock.CContentArea.center + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.IP\ Catalog + + true + + id + index + placeholder + + 0 + 0 + dock.single.IP\ Catalog + + + + + + + + + IP\ Catalog + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + true + + id + index + placeholder + + 0 + 0 + dock.single.Hierarchy + + + + + + + + + Hierarchy + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.System\ Contents + + true + + id + index + placeholder + + 0 + 0 + dock.single.System\ Contents + + + + dock.single.Address\ Map + + true + + id + index + placeholder + + 1 + 1 + dock.single.Address\ Map + + + + dock.single.Instrumentation + + true + + id + index + placeholder + + 2 + 2 + dock.single.Instrumentation + + + + dock.single.Clock\ Settings + + true + + id + index + placeholder + + 3 + 3 + dock.single.Clock\ Settings + + + + dock.single.Instance\ Parameters + + true + + id + index + placeholder + + 4 + 4 + dock.single.Instance\ Parameters + + + + dock.single.HDL\ Example + + true + + id + index + placeholder + + 6 + 6 + dock.single.HDL\ Example + + + + dock.single.Generation + + true + + id + index + placeholder + + 7 + 7 + dock.single.Generation + + + + dock.single.Connections + + true + + id + index + placeholder + + 8 + 8 + dock.single.Connections + + + + dock.single.Domains + + true + + id + index + placeholder + + 10 + 10 + dock.single.Domains + + + + + + + + + System Contents + + + + + + + + + + Address Map + + + + + + + + + + Instrumentation + + + + + + + + + + Clock Settings + + + + + + + + + + Instance Parameters + + + + + + + + + + HDL Example + + + + + + + + + + Generation + + + + + + + + + + Connections + + + + + + + + + + Domains + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Parameter\ Editor + + true + + id + index + placeholder + + 0 + 0 + dock.single.Parameter\ Editor + + + + + + + + + Parameter Editor + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Block\ Symbol + + true + + id + index + placeholder + + 0 + 0 + dock.single.Block\ Symbol + + + + dock.single.Element\ Docs + + true + + id + index + placeholder + + 1 + 1 + dock.single.Element\ Docs + + + + + + + + + Block Symbol + + + + + + + + + + Element Docs + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Presets + + true + + id + index + placeholder + + 0 + 0 + dock.single.Presets + + + + + + + + + Presets + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Messages + + true + + id + index + placeholder + + 0 + 0 + dock.single.Messages + + + + + + + + + Messages + + + + + + + + + + + + + + ccontrol west + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + 0 + dock.PlaceholderList + + + dock.single.Device\ Family + + true + + width + x + y + height + + 1061 + 124 + 132 + 311 + + + + + + + + dock.CExternalizeArea + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + + + + dock.single.Address\ Map + + + + + dock.single.Block\ Symbol + + + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol center + true + + false + + + + + dock.single.Generation + dock.single.Clock\ Settings + dock.single.HDL\ Example + dock.single.Instrumentation + dock.single.Domains + + + + + dock.single.Parameter\ Editor + + + + + + + + + dock.single.Clock\ Domains\ \-\ Beta + dock.single.IP\ Catalog + dock.single.Reset\ Domains\ \-\ Beta + + + 0 + dock.PlaceholderList + + + dock.single.IP\ Catalog + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + dock.single.Connections + dock.single.System\ Contents + dock.single.Parameters + dock.single.Assignments + dock.single.Schematic + dock.single.Clocks + dock.single.Interface\ Requirements\ \-\ Alpha + dock.single.Instrumentation\ \-\ Beta + dock.single.Clock\ Domains + dock.single.Interface\ Requirements + dock.single.Interconnect\ Requirements + dock.single.Instrumentation + dock.single.Instance\ Parameters + dock.single.Address\ Map + + + 0 + dock.PlaceholderList + + + dock.single.Parameters + + true + + + + + dock.single.Address\ Map + + + + + dock.single.Assignments + + + + + dock.single.Connections + + + + + dock.single.Instance\ Parameters + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + dock.single.Interconnect\ Requirements + + + + + dock.single.Schematic + + + + + dock.single.System\ Contents + + true + + + + + + + + dock.single.Hierarchy + + + + + + + + dock.single.Messages + dock.single.Generation\ Messages + + + 0 + dock.PlaceholderList + + + dock.single.Messages + + + + + dock.single.Generation\ Messages + + + + + + + dock.single.Element\ Docs + dock.single.Details + dock.single.Block\ Symbol + + + 0 + dock.PlaceholderList + + + dock.single.Details + + true + + + + + dock.single.Block\ Symbol + + true + + + + + dock.single.Messages + + true + + + + + + + + dock.single.Presets + dock.single.Device\ Family + + + 0 + dock.PlaceholderList + + + dock.single.Presets + + + + + dock.single.Device\ Family + + + + + + + + + + + + + dock.CContentArea.center + + + + + + + + Presets + + + + + + + + + + IP Catalog + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Parameters + + true + + index + id + placeholder + + 0 + 0 + dock.single.Parameters + + + + dock.single.Address\ Map + + + + + dock.single.Assignments + + + + + dock.single.Connections + + + + + dock.single.Instance\ Parameters + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + dock.single.Interconnect\ Requirements + + + + + dock.single.Schematic + + + + + dock.single.System\ Contents + + true + + index + id + placeholder + + 1 + 1 + dock.single.System\ Contents + + + + + + + + + Parameters + + + + + + + + + + System Contents + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Details + + true + + index + id + placeholder + + 0 + 0 + dock.single.Details + + + + dock.single.Block\ Symbol + + true + + index + id + placeholder + + 1 + 1 + dock.single.Block\ Symbol + + + + dock.single.Messages + + true + + index + id + placeholder + + 2 + 2 + dock.single.Messages + + + + + + + + + Details + + + + + + + + + + Block Symbol + + + + + + + + + + Messages + + + + + + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + dock.single.Device\ Family + + + + + dock.single.Parameters + + + + + dock.single.Hierarchy + + + + + dock.single.System\ Contents + + + + + + + + + dock.CContentArea.minimize + + + + + + + + + + dock.single.Assignments + + + + + + + + + + 2 + dock.single.Assignments + + + + + + + Assignments + + + + + + + + + + dock.single.Address\ Map + + + + + + + + + + 1 + dock.single.Address\ Map + + + + + + + Address Map + + + + + + + + + + dock.single.Schematic + + + + + + + + + + 1 + dock.single.Schematic + + + + + + + Schematic + + + + + + + + + + dock.single.Device\ Family + + + + + + + + + 1 + dock.single.Device\ Family + + + + + + + Device Family + + + + + + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + + 1 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + Clock Domains - Beta + + + + + + + + + + dock.single.Generation\ Messages + + + + + + + + + 1 + dock.single.Generation\ Messages + + + + + + + Generation Messages + + + + + + + + + + dock.single.Connections + + + + + + + + + + 3 + dock.single.Connections + + + + + + + Connections + + + + + + + + + + dock.single.Interconnect\ Requirements + + + + + + + + + + 1 + dock.single.Interconnect\ Requirements + + + + + + + Interconnect Requirements + + + + + + + + + + dock.single.Instance\ Parameters + + + + + + + + + + 4 + dock.single.Instance\ Parameters + + + + + + + Instance Parameters + + + + + + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + 5 + dock.single.Instrumentation\ \-\ Beta + + + + + + + Instrumentation - Beta + + + + + + + + + + dock.single.Hierarchy + + + + + + + + + + + + + + + Hierarchy + + + + + + + + + + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + + + + + 2 + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + Reset Domains - Beta + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Details + + + + + + + + + + 0 + dock.single.Details + + + + + + + + dock.mode.minimized + dock.mode.maximized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Parameters + + + + + dock.mode.normal + ccontrol center + + + dock.single.Parameters + + + + + + + + + + 0 + dock.single.Parameters + + + + + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Address\ Map + + + + + dock.mode.normal + ccontrol center + + + dock.single.Address\ Map + + + + + + + + + + 2 + dock.single.Address\ Map + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Schematic + + + + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Presets + + + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Messages + + + + + + + + + + + + + + + dock.mode.externalized + dock.mode.minimized + dock.mode.maximized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + dock.mode.externalized + external + + + 124 + 132 + 1061 + 311 + false + dock.single.Device\ Family + + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Device\ Family + + + + + dock.mode.normal + ccontrol center + + + dock.single.Device\ Family + + + + + + + + + + + 1 + dock.single.Device\ Family + + + + + + + + dock.mode.maximized + dock.mode.minimized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + 0 + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Clock\ Domains\ \-\ Beta + + + 0 + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.mode.normal + ccontrol center + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + 1 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Generation\ Messages + + + + + + + + + 1 + dock.single.Generation\ Messages + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Connections + + + + + + + + + + 8 + dock.single.Connections + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.minimized + ccontrol west + + + 1 + false + 978 + dock.single.System\ Contents + + + + + dock.mode.normal + ccontrol center + + + dock.single.System\ Contents + + + + + + + + + + 1 + dock.single.System\ Contents + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Interconnect\ Requirements + + + + + + + + + + 5 + dock.single.Interconnect\ Requirements + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + 8 + dock.single.Instrumentation\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instance\ Parameters + + + + + + + + + + 8 + dock.single.Instance\ Parameters + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.IP\ Catalog + + + + + + + + + + + + + + + dock.mode.minimized + dock.mode.maximized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Hierarchy + + + + + dock.mode.normal + ccontrol center + + + dock.single.Hierarchy + + + + + + + + + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Block\ Symbol + + + + + dock.mode.normal + ccontrol center + + + dock.single.Block\ Symbol + + + + + + + + + 1 + dock.single.Block\ Symbol + + + + + + + + dock.mode.maximized + dock.mode.minimized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + 1 + dock.single.Reset\ Domains\ \-\ Beta + + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Reset\ Domains\ \-\ Beta + + + 1 + dock.single.Reset\ Domains\ \-\ Beta + + + + + dock.mode.normal + ccontrol center + + + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + + 1 + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Quartus/Design/.qsys_edit/UART_schematic.nlv b/Quartus/Design/.qsys_edit/UART_schematic.nlv new file mode 100644 index 0000000..e0e8e88 --- /dev/null +++ b/Quartus/Design/.qsys_edit/UART_schematic.nlv @@ -0,0 +1,14 @@ +# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35 +# +preplace inst UART -pg 1 -lvl 1 -y 40 -regy -20 +preplace inst UART.rs232_0 -pg 1 -lvl 1 -y 100 +preplace inst UART.clk_0 -pg 1 -lvl 1 -y 30 +preplace netloc EXPORTUART(SLAVE)UART.reset,(SLAVE)clk_0.clk_in_reset) 1 0 1 NJ +preplace netloc EXPORTUART(SLAVE)UART.rs232_0_external_interface,(SLAVE)rs232_0.external_interface) 1 0 1 NJ +preplace netloc EXPORTUART(SLAVE)UART.clk,(SLAVE)clk_0.clk_in) 1 0 1 NJ +preplace netloc EXPORTUART(SLAVE)rs232_0.clk,(SLAVE)UART.rs232_0_clk) 1 0 1 NJ +preplace netloc EXPORTUART(SLAVE)UART.rs232_0_reset,(SLAVE)rs232_0.reset) 1 0 1 NJ +preplace netloc EXPORTUART(MASTER)UART.rs232_0_avalon_data_receive_source,(MASTER)rs232_0.avalon_data_receive_source) 1 1 1 N +preplace netloc EXPORTUART(SLAVE)UART.rs232_0_avalon_data_transmit_sink,(SLAVE)rs232_0.avalon_data_transmit_sink) 1 0 1 NJ +levelinfo -pg 1 0 200 680 +levelinfo -hier UART 210 240 460 diff --git a/Quartus/Design/.qsys_edit/filters.xml b/Quartus/Design/.qsys_edit/filters.xml new file mode 100644 index 0000000..99d751b --- /dev/null +++ b/Quartus/Design/.qsys_edit/filters.xml @@ -0,0 +1,2 @@ + + diff --git a/Quartus/Design/.qsys_edit/preferences.xml b/Quartus/Design/.qsys_edit/preferences.xml new file mode 100644 index 0000000..7d2bdc4 --- /dev/null +++ b/Quartus/Design/.qsys_edit/preferences.xml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + diff --git a/Quartus/Design/.qsys_edit/uart_screen.xml b/Quartus/Design/.qsys_edit/uart_screen.xml new file mode 100644 index 0000000..16f3996 --- /dev/null +++ b/Quartus/Design/.qsys_edit/uart_screen.xml @@ -0,0 +1,2208 @@ + + + + eclipse + + + + + + + + + + + + ccontrol north + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + external + true + + + 0 + dock.PlaceholderList + + + + + + + dock.CExternalizeArea + + + + + + + + + ccontrol south + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol east + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol center + true + + false + + + + + + + + + + + + + + + + + + + + + + + + + dock.CContentArea.center + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.IP\ Catalog + + true + + id + index + placeholder + + 0 + 0 + dock.single.IP\ Catalog + + + + + + + + + IP\ Catalog + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + true + + id + index + placeholder + + 0 + 0 + dock.single.Hierarchy + + + + + + + + + Hierarchy + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.System\ Contents + + true + + id + index + placeholder + + 0 + 0 + dock.single.System\ Contents + + + + dock.single.Address\ Map + + true + + id + index + placeholder + + 1 + 1 + dock.single.Address\ Map + + + + dock.single.Instrumentation + + true + + id + index + placeholder + + 2 + 2 + dock.single.Instrumentation + + + + dock.single.Clock\ Settings + + true + + id + index + placeholder + + 3 + 3 + dock.single.Clock\ Settings + + + + dock.single.Instance\ Parameters + + true + + id + index + placeholder + + 4 + 4 + dock.single.Instance\ Parameters + + + + dock.single.HDL\ Example + + true + + id + index + placeholder + + 6 + 6 + dock.single.HDL\ Example + + + + dock.single.Generation + + true + + id + index + placeholder + + 7 + 7 + dock.single.Generation + + + + dock.single.Connections + + true + + id + index + placeholder + + 8 + 8 + dock.single.Connections + + + + dock.single.Domains + + true + + id + index + placeholder + + 10 + 10 + dock.single.Domains + + + + + + + + + System Contents + + + + + + + + + + Address Map + + + + + + + + + + Instrumentation + + + + + + + + + + Clock Settings + + + + + + + + + + Instance Parameters + + + + + + + + + + HDL Example + + + + + + + + + + Generation + + + + + + + + + + Connections + + + + + + + + + + Domains + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Parameter\ Editor + + true + + id + index + placeholder + + 0 + 0 + dock.single.Parameter\ Editor + + + + + + + + + Parameter Editor + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Block\ Symbol + + true + + id + index + placeholder + + 0 + 0 + dock.single.Block\ Symbol + + + + dock.single.Element\ Docs + + true + + id + index + placeholder + + 1 + 1 + dock.single.Element\ Docs + + + + + + + + + Block Symbol + + + + + + + + + + Element Docs + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Presets + + true + + id + index + placeholder + + 0 + 0 + dock.single.Presets + + + + + + + + + Presets + + + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Messages + + true + + id + index + placeholder + + 0 + 0 + dock.single.Messages + + + + + + + + + Messages + + + + + + + + + + + + + + ccontrol west + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + + + 0 + dock.PlaceholderList + + + dock.single.Device\ Family + + true + + width + x + y + height + + 1061 + 124 + 132 + 311 + + + + + + + + dock.CExternalizeArea + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + dock.single.Hierarchy + + + + + dock.single.Address\ Map + + + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + + + + + dock.CContentArea.minimize + + + + + + + + + ccontrol center + true + + false + + + + + dock.single.Generation + dock.single.Clock\ Settings + dock.single.HDL\ Example + dock.single.Instrumentation + dock.single.Domains + + + + + dock.single.Parameter\ Editor + + + + + + + + + + dock.single.Clock\ Domains\ \-\ Beta + dock.single.IP\ Catalog + dock.single.Reset\ Domains\ \-\ Beta + + + 0 + dock.PlaceholderList + + + dock.single.IP\ Catalog + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + dock.single.Hierarchy + + + + + + dock.single.Connections + dock.single.Parameters + dock.single.Assignments + dock.single.Schematic + dock.single.Clocks + dock.single.Interface\ Requirements\ \-\ Alpha + dock.single.Instrumentation\ \-\ Beta + dock.single.Clock\ Domains + dock.single.Interface\ Requirements + dock.single.Interconnect\ Requirements + dock.single.Instrumentation + dock.single.Instance\ Parameters + dock.single.Address\ Map + + + 0 + dock.PlaceholderList + + + dock.single.Parameters + + true + + + + + dock.single.Address\ Map + + + + + dock.single.Assignments + + + + + dock.single.Connections + + + + + dock.single.Instance\ Parameters + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + dock.single.Interconnect\ Requirements + + + + + dock.single.Schematic + + + + + dock.single.System\ Contents + + true + + + + + + + + dock.single.Messages + dock.single.Generation\ Messages + + + 0 + dock.PlaceholderList + + + dock.single.Messages + + + + + dock.single.Generation\ Messages + + + + + + + + + dock.single.Element\ Docs + dock.single.Details + dock.single.Block\ Symbol + + + 0 + dock.PlaceholderList + + + + + dock.single.Presets + dock.single.Device\ Family + + + 0 + dock.PlaceholderList + + + dock.single.Presets + + + + + dock.single.Device\ Family + + + + + + + + + + + + + dock.CContentArea.center + + + + + + + + Messages + + + + + + + + + + Presets + + + + + + + + 0 + + 0 + dock.PlaceholderList + + + dock.single.Details + + true + + index + id + placeholder + + 0 + 0 + dock.single.Details + + + + dock.single.Block\ Symbol + + true + + index + id + placeholder + + 1 + 1 + dock.single.Block\ Symbol + + + + + + + + + Details + + + + + + + + + + Block Symbol + + + + + + + + + + + + IP Catalog + + + + + + + + 1 + + 0 + dock.PlaceholderList + + + dock.single.Parameters + + true + + index + id + placeholder + + 0 + 0 + dock.single.Parameters + + + + dock.single.Address\ Map + + + + + dock.single.Assignments + + + + + dock.single.Connections + + + + + dock.single.Instance\ Parameters + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + dock.single.Interconnect\ Requirements + + + + + dock.single.Schematic + + + + + dock.single.System\ Contents + + true + + index + id + placeholder + + 1 + 1 + dock.single.System\ Contents + + + + + + + + + Parameters + + + + + + + + + + System Contents + + + + + + + + + + + + + + true + + + + 0 + dock.PlaceholderList + + + dock.single.Device\ Family + + + + + dock.single.Parameters + + + + + dock.single.Hierarchy + + + + + dock.single.System\ Contents + + + + + + + + + dock.CContentArea.minimize + + + + + + + + + + dock.single.Assignments + + + + + + + + + + 2 + dock.single.Assignments + + + + + + + Assignments + + + + + + + + + + dock.single.Address\ Map + + + + + + + + + + 1 + dock.single.Address\ Map + + + + + + + Address Map + + + + + + + + + + dock.single.Schematic + + + + + + + + + + 7 + dock.single.Schematic + + + + + + + Schematic + + + + + + + + + + dock.single.Device\ Family + + + + + + + + + 1 + dock.single.Device\ Family + + + + + + + Device Family + + + + + + + + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + + 1 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + Clock Domains - Beta + + + + + + + + + + dock.single.Generation\ Messages + + + + + + + + + 1 + dock.single.Generation\ Messages + + + + + + + Generation Messages + + + + + + + + + + dock.single.Connections + + + + + + + + + + 3 + dock.single.Connections + + + + + + + Connections + + + + + + + + + + dock.single.Interconnect\ Requirements + + + + + + + + + + 1 + dock.single.Interconnect\ Requirements + + + + + + + Interconnect Requirements + + + + + + + + + + dock.single.Instance\ Parameters + + + + + + + + + + 4 + dock.single.Instance\ Parameters + + + + + + + Instance Parameters + + + + + + + + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + 5 + dock.single.Instrumentation\ \-\ Beta + + + + + + + Instrumentation - Beta + + + + + + + + + + dock.single.Hierarchy + + + + + + + + + + + + + + + Hierarchy + + + + + + + + + + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + + + + + 2 + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + Reset Domains - Beta + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Details + + + + + + + + + + 0 + dock.single.Details + + + + + + + + dock.mode.minimized + dock.mode.maximized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Parameters + + + + + dock.mode.normal + ccontrol center + + + dock.single.Parameters + + + + + + + + + + + 0 + dock.single.Parameters + + + + + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Address\ Map + + + + + dock.mode.normal + ccontrol center + + + dock.single.Address\ Map + + + + + + + + + + 2 + dock.single.Address\ Map + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Schematic + + + + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Presets + + + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Messages + + + + + + + + + + + + + + dock.mode.externalized + dock.mode.minimized + dock.mode.maximized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + dock.mode.externalized + external + + + 124 + 132 + 1061 + 311 + false + dock.single.Device\ Family + + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Device\ Family + + + + + dock.mode.normal + ccontrol center + + + dock.single.Device\ Family + + + + + + + + + + + 1 + dock.single.Device\ Family + + + + + + + + dock.mode.maximized + dock.mode.minimized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + 0 + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Clock\ Domains\ \-\ Beta + + + 0 + dock.single.Clock\ Domains\ \-\ Beta + + + + + dock.mode.normal + ccontrol center + + + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + + + 1 + dock.single.Clock\ Domains\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Generation\ Messages + + + + + + + + + 1 + dock.single.Generation\ Messages + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Connections + + + + + + + + + + 8 + dock.single.Connections + + + + + + + + dock.mode.minimized + dock.mode.normal + + + + dock.mode.minimized + ccontrol west + + + 1 + false + 978 + dock.single.System\ Contents + + + + + dock.mode.normal + ccontrol center + + + dock.single.System\ Contents + + + + + + + + + + + 1 + dock.single.System\ Contents + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Interconnect\ Requirements + + + + + + + + + + 5 + dock.single.Interconnect\ Requirements + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instrumentation\ \-\ Beta + + + + + + + + + + 8 + dock.single.Instrumentation\ \-\ Beta + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Instance\ Parameters + + + + + + + + + + 8 + dock.single.Instance\ Parameters + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.IP\ Catalog + + + + + + + + + + + + + + + dock.mode.minimized + dock.mode.maximized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + dock.mode.minimized + ccontrol west + + + 0 + false + 400 + dock.single.Hierarchy + + + + + dock.mode.normal + ccontrol center + + + dock.single.Hierarchy + + + + + + + + + + + + + + + + dock.mode.normal + + + + dock.mode.normal + ccontrol center + + + dock.single.Block\ Symbol + + + + + + + + + + 0 + dock.single.Block\ Symbol + + + + + + + + dock.mode.maximized + dock.mode.minimized + dock.mode.normal + + + + dock.mode.maximized + ccontrol center + + + + 1 + dock.single.Reset\ Domains\ \-\ Beta + + + + + dock.mode.minimized + ccontrol north + + + 0 + false + 400 + dock.single.Reset\ Domains\ \-\ Beta + + + 1 + dock.single.Reset\ Domains\ \-\ Beta + + + + + dock.mode.normal + ccontrol center + + + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + + 1 + dock.single.Reset\ Domains\ \-\ Beta + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv b/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv new file mode 100644 index 0000000..8c3ff98 --- /dev/null +++ b/Quartus/Design/.qsys_edit/uart_screen_schematic.nlv @@ -0,0 +1,11 @@ +# # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35 +# +preplace inst unsaved.rs232_0 -pg 1 -lvl 1 -y 30 +preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20 +preplace netloc EXPORTunsaved(SLAVE)unsaved.clk,(SLAVE)rs232_0.clk) 1 0 1 NJ +preplace netloc EXPORTunsaved(SLAVE)unsaved.interrupt,(SLAVE)rs232_0.interrupt) 1 0 1 NJ +preplace netloc EXPORTunsaved(SLAVE)unsaved.reset,(SLAVE)rs232_0.reset) 1 0 1 NJ +preplace netloc EXPORTunsaved(SLAVE)unsaved.avalon_rs232_slave,(SLAVE)rs232_0.avalon_rs232_slave) 1 0 1 NJ +preplace netloc EXPORTunsaved(SLAVE)unsaved.external_interface,(SLAVE)rs232_0.external_interface) 1 0 1 NJ +levelinfo -pg 1 0 120 320 +levelinfo -hier unsaved 130 160 310 diff --git a/Quartus/Design/UART.sopcinfo b/Quartus/Design/UART.sopcinfo new file mode 100644 index 0000000..5a714b5 --- /dev/null +++ b/Quartus/Design/UART.sopcinfo @@ -0,0 +1,1057 @@ + + + + + + + java.lang.Integer + 1653392842 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + EP4CE6E22C8 + false + true + false + true + DEVICE + + + java.lang.String + 8 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + rs232_0_clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + rs232_0_clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + rs232_0_clk + + + java.lang.String + Cyclone IV E + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + long + 5000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 5000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 5000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + double + 0.0 + true + false + false + true + + + java.lang.String + Streaming + false + true + true + true + + + int + 115200 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 0 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + Cyclone IV E + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + from_uart_ready + Input + 1 + ready + + + from_uart_data + Output + 8 + data + + + from_uart_error + Output + 1 + error + + + from_uart_valid + Output + 1 + valid + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + to_uart_data + Input + 8 + data + + + to_uart_error + Input + 1 + error + + + to_uart_valid + Input + 1 + valid + + + to_uart_ready + Output + 1 + ready + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + UART_RXD + Input + 1 + export + + + UART_TXD + Output + 1 + export + + + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 21.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 21.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 21.1 + + + 1 + altera_up_avalon_rs232 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + RS232 UART + 17.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 21.1 + + + 1 + avalon_streaming_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink + 21.1 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 21.1 + + 21.1 842 + + diff --git a/Quartus/Design/UART/UART.bsf b/Quartus/Design/UART/UART.bsf new file mode 100644 index 0000000..c0fcb92 --- /dev/null +++ b/Quartus/Design/UART/UART.bsf @@ -0,0 +1,171 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2021 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 544 368) + (text "UART" (rect 255 -1 284 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 352 20 364)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 224 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 224 112)(line_width 1)) + ) + (port + (pt 544 72) + (input) + (text "rs232_0_from_uart_ready" (rect 0 0 109 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_ready" (rect 410 61 548 72)(font "Arial" (font_size 8))) + (line (pt 544 72)(pt 304 72)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "rs232_0_to_uart_data[7..0]" (rect 0 0 109 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_data[7..0]" (rect 4 141 160 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 224 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "rs232_0_to_uart_error" (rect 0 0 93 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_error" (rect 4 157 130 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 224 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "rs232_0_to_uart_valid" (rect 0 0 90 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_valid" (rect 4 173 130 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 224 184)(line_width 1)) + ) + (port + (pt 0 240) + (input) + (text "rs232_0_clk" (rect 0 0 49 12)(font "Arial" (font_size 8))) + (text "rs232_0_clk" (rect 4 229 70 240)(font "Arial" (font_size 8))) + (line (pt 0 240)(pt 224 240)(line_width 1)) + ) + (port + (pt 0 280) + (input) + (text "rs232_0_UART_RXD" (rect 0 0 95 12)(font "Arial" (font_size 8))) + (text "rs232_0_UART_RXD" (rect 4 269 100 280)(font "Arial" (font_size 8))) + (line (pt 0 280)(pt 224 280)(line_width 1)) + ) + (port + (pt 0 336) + (input) + (text "rs232_0_reset" (rect 0 0 59 12)(font "Arial" (font_size 8))) + (text "rs232_0_reset" (rect 4 325 82 336)(font "Arial" (font_size 8))) + (line (pt 0 336)(pt 224 336)(line_width 1)) + ) + (port + (pt 544 88) + (output) + (text "rs232_0_from_uart_data[7..0]" (rect 0 0 122 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_data[7..0]" (rect 393 77 561 88)(font "Arial" (font_size 8))) + (line (pt 544 88)(pt 304 88)(line_width 3)) + ) + (port + (pt 544 104) + (output) + (text "rs232_0_from_uart_error" (rect 0 0 106 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_error" (rect 414 93 552 104)(font "Arial" (font_size 8))) + (line (pt 544 104)(pt 304 104)(line_width 1)) + ) + (port + (pt 544 120) + (output) + (text "rs232_0_from_uart_valid" (rect 0 0 103 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_valid" (rect 416 109 554 120)(font "Arial" (font_size 8))) + (line (pt 544 120)(pt 304 120)(line_width 1)) + ) + (port + (pt 0 200) + (output) + (text "rs232_0_to_uart_ready" (rect 0 0 96 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_ready" (rect 4 189 130 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 224 200)(line_width 1)) + ) + (port + (pt 0 296) + (output) + (text "rs232_0_UART_TXD" (rect 0 0 93 12)(font "Arial" (font_size 8))) + (text "rs232_0_UART_TXD" (rect 4 285 100 296)(font "Arial" (font_size 8))) + (line (pt 0 296)(pt 224 296)(line_width 1)) + ) + (drawing + (text "clk" (rect 209 43 436 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 229 67 476 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 195 83 420 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 229 107 500 224)(font "Arial" (color 0 0 0))) + (text "rs232_0_avalon_data_receive_source" (rect 305 43 814 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "ready" (rect 276 67 582 144)(font "Arial" (color 0 0 0))) + (text "data" (rect 283 83 590 176)(font "Arial" (color 0 0 0))) + (text "error" (rect 279 99 588 208)(font "Arial" (color 0 0 0))) + (text "valid" (rect 281 115 592 240)(font "Arial" (color 0 0 0))) + (text "rs232_0_avalon_data_transmit_sink" (rect 11 123 220 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "data" (rect 229 147 482 304)(font "Arial" (color 0 0 0))) + (text "error" (rect 229 163 488 336)(font "Arial" (color 0 0 0))) + (text "valid" (rect 229 179 488 368)(font "Arial" (color 0 0 0))) + (text "ready" (rect 229 195 488 400)(font "Arial" (color 0 0 0))) + (text "rs232_0_clk" (rect 153 211 372 435)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 229 235 476 480)(font "Arial" (color 0 0 0))) + (text "rs232_0_external_interface" (rect 64 251 284 515)(font "Arial" (color 128 0 0)(font_size 9))) + (text "RXD" (rect 229 275 476 560)(font "Arial" (color 0 0 0))) + (text "TXD" (rect 229 291 476 592)(font "Arial" (color 0 0 0))) + (text "rs232_0_reset" (rect 139 307 356 627)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 229 331 488 672)(font "Arial" (color 0 0 0))) + (text " UART " (rect 512 352 1060 714)(font "Arial" )) + (line (pt 224 32)(pt 304 32)(line_width 1)) + (line (pt 304 32)(pt 304 352)(line_width 1)) + (line (pt 224 352)(pt 304 352)(line_width 1)) + (line (pt 224 32)(pt 224 352)(line_width 1)) + (line (pt 225 52)(pt 225 76)(line_width 1)) + (line (pt 226 52)(pt 226 76)(line_width 1)) + (line (pt 225 92)(pt 225 116)(line_width 1)) + (line (pt 226 92)(pt 226 116)(line_width 1)) + (line (pt 303 52)(pt 303 124)(line_width 1)) + (line (pt 302 52)(pt 302 124)(line_width 1)) + (line (pt 225 132)(pt 225 204)(line_width 1)) + (line (pt 226 132)(pt 226 204)(line_width 1)) + (line (pt 225 220)(pt 225 244)(line_width 1)) + (line (pt 226 220)(pt 226 244)(line_width 1)) + (line (pt 225 260)(pt 225 300)(line_width 1)) + (line (pt 226 260)(pt 226 300)(line_width 1)) + (line (pt 225 316)(pt 225 340)(line_width 1)) + (line (pt 226 316)(pt 226 340)(line_width 1)) + (line (pt 0 0)(pt 544 0)(line_width 1)) + (line (pt 544 0)(pt 544 368)(line_width 1)) + (line (pt 0 368)(pt 544 368)(line_width 1)) + (line (pt 0 0)(pt 0 368)(line_width 1)) + ) +) diff --git a/Quartus/Design/UART/UART.cmp b/Quartus/Design/UART/UART.cmp new file mode 100644 index 0000000..3878e10 --- /dev/null +++ b/Quartus/Design/UART/UART.cmp @@ -0,0 +1,19 @@ + component UART is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + rs232_0_from_uart_ready : in std_logic := 'X'; -- ready + rs232_0_from_uart_data : out std_logic_vector(7 downto 0); -- data + rs232_0_from_uart_error : out std_logic; -- error + rs232_0_from_uart_valid : out std_logic; -- valid + rs232_0_to_uart_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data + rs232_0_to_uart_error : in std_logic := 'X'; -- error + rs232_0_to_uart_valid : in std_logic := 'X'; -- valid + rs232_0_to_uart_ready : out std_logic; -- ready + rs232_0_clk : in std_logic := 'X'; -- clk + rs232_0_UART_RXD : in std_logic := 'X'; -- RXD + rs232_0_UART_TXD : out std_logic; -- TXD + rs232_0_reset : in std_logic := 'X' -- reset + ); + end component UART; + diff --git a/Quartus/Design/UART/UART.html b/Quartus/Design/UART/UART.html new file mode 100644 index 0000000..2337193 --- /dev/null +++ b/Quartus/Design/UART/UART.html @@ -0,0 +1,216 @@ + + + + + datasheet for UART + + + + + + + + +
UART +
+
+
+ + + + + +
2022.05.24.19:47:23Datasheet
+
+
Overview
+
+
+ + + + + + + + +
  clk_0 UART
+
+
+
+
+
+
+
Memory Map
+ + + + +
+ +
+
+

clk_0

clock_source v21.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +
clockFrequency5000000
clockFrequencyKnowntrue
inputClockFrequency0
resetSynchronousEdgesNONE
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

rs232_0

altera_up_avalon_rs232 v17.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ref_clk_freq0.0
avalon_bus_typeStreaming
baud115200
parityNone
data_bits8
stop_bits1
AUTO_DEVICE_FAMILYCYCLONEIVE
AUTO_CLK_CLOCK_RATE0
deviceFamilyCyclone IV E
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.00 seconds
+ + diff --git a/Quartus/Design/UART/UART.xml b/Quartus/Design/UART/UART.xml new file mode 100644 index 0000000..dfa7b08 --- /dev/null +++ b/Quartus/Design/UART/UART.xml @@ -0,0 +1,293 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 0 starting:UART "UART" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 2 modules, 0 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + UART" reuses altera_up_avalon_rs232 "submodules/UART_rs232_0"]]> + queue size: 0 starting:altera_up_avalon_rs232 "submodules/UART_rs232_0" + Starting Generation of RS232 UART + The input clock frequency must be known at generation time. + UART" instantiated altera_up_avalon_rs232 "rs232_0"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 0 starting:altera_up_avalon_rs232 "submodules/UART_rs232_0" + Starting Generation of RS232 UART + The input clock frequency must be known at generation time. + UART" instantiated altera_up_avalon_rs232 "rs232_0"]]> + + + diff --git a/Quartus/Design/UART/UART_bb.v b/Quartus/Design/UART/UART_bb.v new file mode 100644 index 0000000..aa5f99d --- /dev/null +++ b/Quartus/Design/UART/UART_bb.v @@ -0,0 +1,32 @@ + +module UART ( + rs232_0_clk, + rs232_0_reset, + rs232_0_UART_RXD, + rs232_0_UART_TXD, + rs232_0_from_uart_ready, + rs232_0_from_uart_data, + rs232_0_from_uart_error, + rs232_0_from_uart_valid, + rs232_0_to_uart_data, + rs232_0_to_uart_error, + rs232_0_to_uart_valid, + rs232_0_to_uart_ready, + clk_clk, + reset_reset_n); + + input rs232_0_clk; + input rs232_0_reset; + input rs232_0_UART_RXD; + output rs232_0_UART_TXD; + input rs232_0_from_uart_ready; + output [7:0] rs232_0_from_uart_data; + output rs232_0_from_uart_error; + output rs232_0_from_uart_valid; + input [7:0] rs232_0_to_uart_data; + input rs232_0_to_uart_error; + input rs232_0_to_uart_valid; + output rs232_0_to_uart_ready; + input clk_clk; + input reset_reset_n; +endmodule diff --git a/Quartus/Design/UART/UART_generation.rpt b/Quartus/Design/UART/UART_generation.rpt new file mode 100644 index 0000000..6e99cb0 --- /dev/null +++ b/Quartus/Design/UART/UART_generation.rpt @@ -0,0 +1,34 @@ +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/UART.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: qsys-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/UART.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: UART: Generating UART "UART" for QUARTUS_SYNTH +Info: rs232_0: Starting Generation of RS232 UART +Error: rs232_0: The input clock frequency must be known at generation time. +Info: rs232_0: "UART" instantiated altera_up_avalon_rs232 "rs232_0" +Info: UART: Done "UART" with 2 modules, 6 files +Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings +Info: Finished: Create HDL design files for synthesis diff --git a/Quartus/Design/UART/UART_generation_previous.rpt b/Quartus/Design/UART/UART_generation_previous.rpt new file mode 100644 index 0000000..e8be8c5 --- /dev/null +++ b/Quartus/Design/UART/UART_generation_previous.rpt @@ -0,0 +1,36 @@ +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/UART.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem. +Info: qsys-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/UART.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem. +Info: UART: Generating UART "UART" for QUARTUS_SYNTH +Info: rs232_0: Starting Generation of RS232 UART +Error: rs232_0: The input clock frequency must be known at generation time. +Info: rs232_0: "UART" instantiated altera_up_avalon_rs232 "rs232_0" +Info: UART: Done "UART" with 2 modules, 6 files +Error: qsys-generate failed with exit code 1: 1 Error, 1 Warning +Info: Finished: Create HDL design files for synthesis diff --git a/Quartus/Design/UART/UART_inst.v b/Quartus/Design/UART/UART_inst.v new file mode 100644 index 0000000..590069c --- /dev/null +++ b/Quartus/Design/UART/UART_inst.v @@ -0,0 +1,17 @@ + UART u0 ( + .rs232_0_clk (), // rs232_0_clk.clk + .rs232_0_reset (), // rs232_0_reset.reset + .rs232_0_UART_RXD (), // rs232_0_external_interface.RXD + .rs232_0_UART_TXD (), // .TXD + .rs232_0_from_uart_ready (), // rs232_0_avalon_data_receive_source.ready + .rs232_0_from_uart_data (), // .data + .rs232_0_from_uart_error (), // .error + .rs232_0_from_uart_valid (), // .valid + .rs232_0_to_uart_data (), // rs232_0_avalon_data_transmit_sink.data + .rs232_0_to_uart_error (), // .error + .rs232_0_to_uart_valid (), // .valid + .rs232_0_to_uart_ready (), // .ready + .clk_clk (), // clk.clk + .reset_reset_n () // reset.reset_n + ); + diff --git a/Quartus/Design/UART/synthesis/UART.debuginfo b/Quartus/Design/UART/synthesis/UART.debuginfo new file mode 100644 index 0000000..2b172f9 --- /dev/null +++ b/Quartus/Design/UART/synthesis/UART.debuginfo @@ -0,0 +1,1079 @@ + + + + + + + com.altera.sopcmodel.ensemble.EClockAdapter + HANDSHAKE + false + true + true + true + + + java.lang.String + EP4CE6E22C8 + false + true + true + true + + + java.lang.String + CYCLONEIVE + false + true + true + true + + + java.lang.String + 8 + false + true + false + true + + + com.altera.sopcmodel.ensemble.Ensemble$EFabricMode + QSYS + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1653392842 + false + true + true + true + + + boolean + false + false + true + false + true + + + com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage + VERILOG + false + false + false + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.definition.BoundaryDefinition + + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + long + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + + + long + 5000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 5000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 5000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + double + 0.0 + true + false + false + true + + + java.lang.String + Streaming + false + true + true + true + + + int + 115200 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 0 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + Cyclone IV E + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + false + true + true + false + true + + + java.lang.Long + 0 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + from_uart_ready + Input + 1 + ready + + + from_uart_data + Output + 8 + data + + + from_uart_error + Output + 1 + error + + + from_uart_valid + Output + 1 + valid + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + to_uart_data + Input + 8 + data + + + to_uart_error + Input + 1 + error + + + to_uart_valid + Input + 1 + valid + + + to_uart_ready + Output + 1 + ready + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + UART_RXD + Input + 1 + export + + + UART_TXD + Output + 1 + export + + + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 21.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 21.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 21.1 + + + 1 + altera_up_avalon_rs232 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + RS232 UART + 17.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 21.1 + + + 1 + avalon_streaming_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink + 21.1 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 21.1 + + 21.1 842 + CCD9AC02D57D00000180F5E4A10B + diff --git a/Quartus/Design/UART/synthesis/UART.qip b/Quartus/Design/UART/synthesis/UART.qip new file mode 100644 index 0000000..b6cbb01 --- /dev/null +++ b/Quartus/Design/UART/synthesis/UART.qip @@ -0,0 +1,48 @@ +set_global_assignment -entity "UART" -library "UART" -name IP_TOOL_NAME "Qsys" +set_global_assignment -entity "UART" -library "UART" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "UART" -library "UART" -name IP_TOOL_ENV "Qsys" +set_global_assignment -library "UART" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../UART.sopcinfo"] +set_global_assignment -entity "UART" -library "UART" -name SLD_INFO "QSYS_NAME UART HAS_SOPCINFO 1 GENERATION_ID 1653392842" +set_global_assignment -library "UART" -name MISC_FILE [file join $::quartus(qip_path) "../UART.cmp"] +set_global_assignment -library "UART" -name SLD_FILE [file join $::quartus(qip_path) "UART.debuginfo"] +set_global_assignment -entity "UART" -library "UART" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" +set_global_assignment -entity "UART" -library "UART" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -entity "UART" -library "UART" -name IP_QSYS_MODE "SYSTEM" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "UART" -name MISC_FILE [file join $::quartus(qip_path) "../../UART.qsys"] +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_NAME "VUFSVA==" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_DISPLAY_NAME "VUFSVA==" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_VERSION "MS4w" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1MzM5Mjg0Mg==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0U2RTIyQzg=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4=" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4=" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19SUzIzMl8wX0NMS19DTE9DS19SQVRF::LTE=::QXV0byBDTE9DS19SQVRF" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19SUzIzMl8wX0NMS19DTE9DS19ET01BSU4=::LTE=::QXV0byBDTE9DS19ET01BSU4=" +set_global_assignment -entity "UART" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19SUzIzMl8wX0NMS19SRVNFVF9ET01BSU4=::LTE=::QXV0byBSRVNFVF9ET01BSU4=" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_NAME "VUFSVF9yczIzMl8w" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_DISPLAY_NAME "UlMyMzIgVUFSVA==" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_AUTHOR "SW50ZWwgRlBHQSBVbml2ZXJzaXR5IFByb2dyYW0=" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_VERSION "MTcuMQ==" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_DESCRIPTION "UlMyMzIgVUFSVCBDb250cm9sbGVy" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "YXZhbG9uX2J1c190eXBl::U3RyZWFtaW5n::QXZhbG9uIFR5cGU=" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "YmF1ZA==::MTE1MjAw::QmF1ZCBSYXRlIChicHMp" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "cGFyaXR5::Tm9uZQ==::UGFyaXR5" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "ZGF0YV9iaXRz::OA==::RGF0YSBCaXRz" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "c3RvcF9iaXRz::MQ==::U3RvcCBCaXRz" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "UART_rs232_0" -library "UART" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::MA==::QXV0byBDTE9DS19SQVRF" + +set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "UART.v"] +set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_counters.v"] +set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_in_deserializer.v"] +set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_out_serializer.v"] +set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_sync_fifo.v"] +set_global_assignment -library "UART" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/UART_rs232_0.v"] diff --git a/Quartus/Design/UART/synthesis/UART.v b/Quartus/Design/UART/synthesis/UART.v new file mode 100644 index 0000000..4892696 --- /dev/null +++ b/Quartus/Design/UART/synthesis/UART.v @@ -0,0 +1,38 @@ +// UART.v + +// Generated using ACDS version 21.1 842 + +`timescale 1 ps / 1 ps +module UART ( + input wire clk_clk, // clk.clk + input wire reset_reset_n, // reset.reset_n + input wire rs232_0_from_uart_ready, // rs232_0_avalon_data_receive_source.ready + output wire [7:0] rs232_0_from_uart_data, // .data + output wire rs232_0_from_uart_error, // .error + output wire rs232_0_from_uart_valid, // .valid + input wire [7:0] rs232_0_to_uart_data, // rs232_0_avalon_data_transmit_sink.data + input wire rs232_0_to_uart_error, // .error + input wire rs232_0_to_uart_valid, // .valid + output wire rs232_0_to_uart_ready, // .ready + input wire rs232_0_clk, // rs232_0_clk.clk + input wire rs232_0_UART_RXD, // rs232_0_external_interface.RXD + output wire rs232_0_UART_TXD, // .TXD + input wire rs232_0_reset // rs232_0_reset.reset + ); + + UART_rs232_0 rs232_0 ( + .clk (rs232_0_clk), // clk.clk + .reset (rs232_0_reset), // reset.reset + .from_uart_ready (rs232_0_from_uart_ready), // avalon_data_receive_source.ready + .from_uart_data (rs232_0_from_uart_data), // .data + .from_uart_error (rs232_0_from_uart_error), // .error + .from_uart_valid (rs232_0_from_uart_valid), // .valid + .to_uart_data (rs232_0_to_uart_data), // avalon_data_transmit_sink.data + .to_uart_error (rs232_0_to_uart_error), // .error + .to_uart_valid (rs232_0_to_uart_valid), // .valid + .to_uart_ready (rs232_0_to_uart_ready), // .ready + .UART_RXD (rs232_0_UART_RXD), // external_interface.export + .UART_TXD (rs232_0_UART_TXD) // .export + ); + +endmodule diff --git a/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v b/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v new file mode 100644 index 0000000..22b9142 --- /dev/null +++ b/Quartus/Design/UART/synthesis/submodules/UART_rs232_0.v @@ -0,0 +1,187 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module reads and writes data to the RS232 connector on Altera's * + * DE-series Development and Education Boards. * + * * + ******************************************************************************/ + +module UART_rs232_0 ( + // Inputs + clk, + reset, + + from_uart_ready, + + to_uart_data, + to_uart_error, + to_uart_valid, + + UART_RXD, + + // Bidirectionals + + // Outputs + from_uart_data, + from_uart_error, + from_uart_valid, + + to_uart_ready, + + UART_TXD +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 0; // Baud counter width +parameter BAUD_TICK_COUNT = 0; +parameter HALF_BAUD_TICK_COUNT = 0; + +parameter TDW = 10; // Total data width +parameter DW = 8; // Data width +parameter ODD_PARITY = 1'b0; + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input from_uart_ready; + +input [(DW-1):0] to_uart_data; +input to_uart_error; +input to_uart_valid; + +input UART_RXD; + +// Bidirectionals + +// Outputs +output [(DW-1):0] from_uart_data; +output from_uart_error; +output from_uart_valid; + +output to_uart_ready; + +output UART_TXD; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire [(DW-1):0] read_data; + +wire write_data_parity; +wire [ 7: 0] write_space; + +// Internal Registers + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +// Output Registers + +// Internal Registers + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +// Output Assignments +assign from_uart_data = read_data; +assign from_uart_error = 1'b0; + +assign to_uart_ready = (|(write_space)); + +// Internal Assignments +assign write_data_parity = (^(to_uart_data)) ^ ODD_PARITY; + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_in_deserializer RS232_In_Deserializer ( + // Inputs + .clk (clk), + .reset (reset), + + .serial_data_in (UART_RXD), + + .receive_data_en (from_uart_ready), + + // Bidirectionals + + // Outputs + .fifo_read_available (), + + .received_data_valid (from_uart_valid), + .received_data (read_data) +); +defparam + RS232_In_Deserializer.CW = CW, + RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_In_Deserializer.TDW = TDW, + RS232_In_Deserializer.DW = (DW - 1); + +altera_up_rs232_out_serializer RS232_Out_Serializer ( + // Inputs + .clk (clk), + .reset (reset), + + .transmit_data (to_uart_data), + .transmit_data_en (to_uart_valid & to_uart_ready), + + // Bidirectionals + + // Outputs + .fifo_write_space (write_space), + + .serial_data_out (UART_TXD) +); +defparam + RS232_Out_Serializer.CW = CW, + RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_Out_Serializer.TDW = TDW, + RS232_Out_Serializer.DW = (DW - 1); + +endmodule + diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v b/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v new file mode 100644 index 0000000..d9bb0fb --- /dev/null +++ b/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_counters.v @@ -0,0 +1,161 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module reads and writes data to the RS232 connectpr on Altera's * + * DE1 and DE2 Development and Education Boards. * + * * + ******************************************************************************/ + +module altera_up_rs232_counters ( + // Inputs + clk, + reset, + + reset_counters, + + // Bidirectionals + + // Outputs + baud_clock_rising_edge, + baud_clock_falling_edge, + all_bits_transmitted +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // BAUD COUNTER WIDTH +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // TOTAL DATA WIDTH + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input reset_counters; + +// Bidirectionals + +// Outputs +output reg baud_clock_rising_edge; +output reg baud_clock_falling_edge; +output reg all_bits_transmitted; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires + +// Internal Registers +reg [(CW-1):0] baud_counter; +reg [ 3: 0] bit_counter; + +// State Machine Registers + + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + baud_counter <= {CW{1'b0}}; + else if (reset_counters) + baud_counter <= {CW{1'b0}}; + else if (baud_counter == BAUD_TICK_COUNT) + baud_counter <= {CW{1'b0}}; + else + baud_counter <= baud_counter + 1; +end + +always @(posedge clk) +begin + if (reset) + baud_clock_rising_edge <= 1'b0; + else if (baud_counter == BAUD_TICK_COUNT) + baud_clock_rising_edge <= 1'b1; + else + baud_clock_rising_edge <= 1'b0; +end + +always @(posedge clk) +begin + if (reset) + baud_clock_falling_edge <= 1'b0; + else if (baud_counter == HALF_BAUD_TICK_COUNT) + baud_clock_falling_edge <= 1'b1; + else + baud_clock_falling_edge <= 1'b0; +end + +always @(posedge clk) +begin + if (reset) + bit_counter <= 4'h0; + else if (reset_counters) + bit_counter <= 4'h0; + else if (bit_counter == TDW) + bit_counter <= 4'h0; + else if (baud_counter == BAUD_TICK_COUNT) + bit_counter <= bit_counter + 4'h1; +end + +always @(posedge clk) +begin + if (reset) + all_bits_transmitted <= 1'b0; + else if (bit_counter == TDW) + all_bits_transmitted <= 1'b1; + else + all_bits_transmitted <= 1'b0; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +endmodule + diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v b/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v new file mode 100644 index 0000000..ef294ef --- /dev/null +++ b/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_in_deserializer.v @@ -0,0 +1,194 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module reads data to the RS232 UART Port. * + * * + ******************************************************************************/ + +module altera_up_rs232_in_deserializer ( + // Inputs + clk, + reset, + + serial_data_in, + + receive_data_en, + + // Bidirectionals + + // Outputs + fifo_read_available, + + received_data_valid, + received_data +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // Baud counter width +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // Total data width +parameter DW = 9; // Data width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input serial_data_in; + +input receive_data_en; + +// Bidirectionals + +// Outputs +output reg [ 7: 0] fifo_read_available; + +output received_data_valid; +output [DW: 0] received_data; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire shift_data_reg_en; +wire all_bits_received; + +wire fifo_is_empty; +wire fifo_is_full; +wire [ 6: 0] fifo_used; + +// Internal Registers +reg receiving_data; + +reg [(TDW-1):0] data_in_shift_reg; + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + fifo_read_available <= 8'h00; + else + fifo_read_available <= {fifo_is_full, fifo_used}; +end + +always @(posedge clk) +begin + if (reset) + receiving_data <= 1'b0; + else if (all_bits_received) + receiving_data <= 1'b0; + else if (serial_data_in == 1'b0) + receiving_data <= 1'b1; +end + +always @(posedge clk) +begin + if (reset) + data_in_shift_reg <= {TDW{1'b0}}; + else if (shift_data_reg_en) + data_in_shift_reg <= + {serial_data_in, data_in_shift_reg[(TDW - 1):1]}; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +// Output assignments +assign received_data_valid = ~fifo_is_empty; + +// Input assignments + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_counters RS232_In_Counters ( + // Inputs + .clk (clk), + .reset (reset), + + .reset_counters (~receiving_data), + + // Bidirectionals + + // Outputs + .baud_clock_rising_edge (), + .baud_clock_falling_edge (shift_data_reg_en), + .all_bits_transmitted (all_bits_received) +); +defparam + RS232_In_Counters.CW = CW, + RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_In_Counters.TDW = TDW; + +altera_up_sync_fifo RS232_In_FIFO ( + // Inputs + .clk (clk), + .reset (reset), + + .write_en (all_bits_received & ~fifo_is_full), + .write_data (data_in_shift_reg[(DW + 1):1]), + + .read_en (receive_data_en & ~fifo_is_empty), + + // Bidirectionals + + // Outputs + .fifo_is_empty (fifo_is_empty), + .fifo_is_full (fifo_is_full), + .words_used (fifo_used), + + .read_data (received_data) +); +defparam + RS232_In_FIFO.DW = DW, + RS232_In_FIFO.DATA_DEPTH = 128, + RS232_In_FIFO.AW = 6; + +endmodule + diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v b/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v new file mode 100644 index 0000000..12250bf --- /dev/null +++ b/Quartus/Design/UART/synthesis/submodules/altera_up_rs232_out_serializer.v @@ -0,0 +1,202 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module writes data to the RS232 UART Port. * + * * + ******************************************************************************/ + +module altera_up_rs232_out_serializer ( + // Inputs + clk, + reset, + + transmit_data, + transmit_data_en, + + // Bidirectionals + + // Outputs + fifo_write_space, + + serial_data_out +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // Baud counter width +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // Total data width +parameter DW = 9; // Data width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input [DW: 0] transmit_data; +input transmit_data_en; + +// Bidirectionals + +// Outputs +output reg [ 7: 0] fifo_write_space; + +output reg serial_data_out; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire shift_data_reg_en; +wire all_bits_transmitted; + +wire read_fifo_en; + +wire fifo_is_empty; +wire fifo_is_full; +wire [ 6: 0] fifo_used; + +wire [DW: 0] data_from_fifo; + +// Internal Registers +reg transmitting_data; + +reg [DW+1:0] data_out_shift_reg; + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + fifo_write_space <= 8'h00; + else + fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used}; +end + + +always @(posedge clk) +begin + if (reset) + serial_data_out <= 1'b1; + else + serial_data_out <= data_out_shift_reg[0]; +end + +always @(posedge clk) +begin + if (reset) + transmitting_data <= 1'b0; + else if (all_bits_transmitted) + transmitting_data <= 1'b0; + else if (fifo_is_empty == 1'b0) + transmitting_data <= 1'b1; +end + +always @(posedge clk) +begin + if (reset) + data_out_shift_reg <= {(DW + 2){1'b1}}; + else if (read_fifo_en) + data_out_shift_reg <= {data_from_fifo, 1'b0}; + else if (shift_data_reg_en) + data_out_shift_reg <= + {1'b1, data_out_shift_reg[DW+1:1]}; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +assign read_fifo_en = + ~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted; + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_counters RS232_Out_Counters ( + // Inputs + .clk (clk), + .reset (reset), + + .reset_counters (~transmitting_data), + + // Bidirectionals + + // Outputs + .baud_clock_rising_edge (shift_data_reg_en), + .baud_clock_falling_edge (), + .all_bits_transmitted (all_bits_transmitted) +); +defparam + RS232_Out_Counters.CW = CW, + RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_Out_Counters.TDW = TDW; + +altera_up_sync_fifo RS232_Out_FIFO ( + // Inputs + .clk (clk), + .reset (reset), + + .write_en (transmit_data_en & ~fifo_is_full), + .write_data (transmit_data), + + .read_en (read_fifo_en), + + // Bidirectionals + + // Outputs + .fifo_is_empty (fifo_is_empty), + .fifo_is_full (fifo_is_full), + .words_used (fifo_used), + + .read_data (data_from_fifo) +); +defparam + RS232_Out_FIFO.DW = DW, + RS232_Out_FIFO.DATA_DEPTH = 128, + RS232_Out_FIFO.AW = 6; + +endmodule + diff --git a/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v b/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v new file mode 100644 index 0000000..6ed843f --- /dev/null +++ b/Quartus/Design/UART/synthesis/submodules/altera_up_sync_fifo.v @@ -0,0 +1,152 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module is a FIFO with same clock for both reads and writes. * + * * + ******************************************************************************/ + +module altera_up_sync_fifo ( + // Inputs + clk, + reset, + + write_en, + write_data, + + read_en, + + // Bidirectionals + + // Outputs + fifo_is_empty, + fifo_is_full, + words_used, + + read_data +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter DW = 31; // Data width +parameter DATA_DEPTH = 128; +parameter AW = 6; // Address width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ + +// Inputs +input clk; +input reset; + +input write_en; +input [DW: 0] write_data; + +input read_en; + +// Bidirectionals + +// Outputs +output fifo_is_empty; +output fifo_is_full; +output [AW: 0] words_used; + +output [DW: 0] read_data; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires + +// Internal Registers + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +scfifo Sync_FIFO ( + // Inputs + .clock (clk), + .sclr (reset), + + .data (write_data), + .wrreq (write_en), + + .rdreq (read_en), + + // Bidirectionals + + // Outputs + .empty (fifo_is_empty), + .full (fifo_is_full), + .usedw (words_used), + + .q (read_data) + + // Unused + // synopsys translate_off + , + .aclr (), + .almost_empty (), + .almost_full () + // synopsys translate_on +); +defparam + Sync_FIFO.add_ram_output_register = "OFF", + Sync_FIFO.intended_device_family = "Cyclone II", + Sync_FIFO.lpm_numwords = DATA_DEPTH, + Sync_FIFO.lpm_showahead = "ON", + Sync_FIFO.lpm_type = "scfifo", + Sync_FIFO.lpm_width = DW + 1, + Sync_FIFO.lpm_widthu = AW + 1, + Sync_FIFO.overflow_checking = "OFF", + Sync_FIFO.underflow_checking = "OFF", + Sync_FIFO.use_eab = "ON"; + +endmodule + diff --git a/Quartus/Design/design.qpf b/Quartus/Design/design.qpf new file mode 100644 index 0000000..f31e6a5 --- /dev/null +++ b/Quartus/Design/design.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2021 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition +# Date created = 19:36:33 五月 24, 2022 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "21.1" +DATE = "19:36:33 五月 24, 2022" + +# Revisions + +PROJECT_REVISION = "design" diff --git a/Quartus/Design/design.qsf b/Quartus/Design/design.qsf new file mode 100644 index 0000000..1ca0cab --- /dev/null +++ b/Quartus/Design/design.qsf @@ -0,0 +1,54 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2021 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition +# Date created = 19:36:33 五月 24, 2022 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# design_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Intel recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE6E22C8 +set_global_assignment -name TOP_LEVEL_ENTITY design +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:36:33 五月 24, 2022" +set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name QSYS_FILE uart_screen.qsys +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE design.v \ No newline at end of file diff --git a/Quartus/Design/design.v b/Quartus/Design/design.v new file mode 100644 index 0000000..bf9e4c8 --- /dev/null +++ b/Quartus/Design/design.v @@ -0,0 +1,14 @@ +uart_screen u0 ( + .clk_clk (), // clk.clk + .reset_reset_n (), // reset.reset_n + .rs232_0_from_uart_ready (), // rs232_0_avalon_data_receive_source.ready + .rs232_0_from_uart_data (), // .data + .rs232_0_from_uart_error (), // .error + .rs232_0_from_uart_valid (), // .valid + .rs232_0_to_uart_data (), // rs232_0_avalon_data_transmit_sink.data + .rs232_0_to_uart_error (), // .error + .rs232_0_to_uart_valid (), // .valid + .rs232_0_to_uart_ready (), // .ready + .rs232_0_UART_RXD (), // rs232_0_external_interface.RXD + .rs232_0_UART_TXD () // .TXD + ); diff --git a/Quartus/Design/uart_screen.qsys b/Quartus/Design/uart_screen.qsys new file mode 100644 index 0000000..d333fb3 --- /dev/null +++ b/Quartus/Design/uart_screen.qsys @@ -0,0 +1,111 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Quartus/Design/uart_screen.sopcinfo b/Quartus/Design/uart_screen.sopcinfo new file mode 100644 index 0000000..8e54700 --- /dev/null +++ b/Quartus/Design/uart_screen.sopcinfo @@ -0,0 +1,1103 @@ + + + + + + + java.lang.Integer + 1653392990 + false + true + false + true + GENERATION_ID + + + java.lang.String + + false + true + false + true + UNIQUE_ID + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + java.lang.String + EP4CE6E22C8 + false + true + false + true + DEVICE + + + java.lang.String + 8 + false + true + false + true + DEVICE_SPEEDGRADE + + + java.lang.Long + -1 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.Integer + -1 + false + true + false + true + CLOCK_DOMAIN + clk + + + java.lang.Integer + -1 + false + true + false + true + RESET_DOMAIN + clk + + + java.lang.String + Cyclone IV E + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + rs232_0 + clk + rs232_0.clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + double + 5.0E7 + true + false + false + true + + + java.lang.String + Streaming + false + true + true + true + + + int + 115200 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + Cyclone IV E + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + from_uart_ready + Input + 1 + ready + + + from_uart_data + Output + 8 + data + + + from_uart_error + Output + 1 + error + + + from_uart_valid + Output + 1 + valid + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + to_uart_data + Input + 8 + data + + + to_uart_error + Input + 1 + error + + + to_uart_valid + Input + 1 + valid + + + to_uart_ready + Output + 1 + ready + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + UART_RXD + Input + 1 + export + + + UART_TXD + Output + 1 + export + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + rs232_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + rs232_0 + reset + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 21.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 21.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 21.1 + + + 1 + altera_up_avalon_rs232 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + RS232 UART + 17.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 21.1 + + + 1 + avalon_streaming_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink + 21.1 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 21.1 + + + 1 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 21.1 + + + 1 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 21.1 + + 21.1 842 + + diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc b/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc new file mode 100644 index 0000000..7b5dc0a --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.sdc @@ -0,0 +1,30 @@ +# (C) 2001-2021 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions and other +# software and tools, and its AMPP partner logic functions, and any output +# files from any of the foregoing (including device programming or simulation +# files), and any associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License Subscription +# Agreement, Intel FPGA IP License Agreement, or other applicable +# license agreement, including, without limitation, that your use is for the +# sole purpose of programming logic devices manufactured by Intel and sold by +# Intel or its authorized distributors. Please refer to the applicable +# agreement for further details. + + +# +--------------------------------------------------- +# | Cut the async clear paths +# +--------------------------------------------------- +set aclr_counter 0 +set clrn_counter 0 +set aclr_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +set clrn_collection [get_pins -compatibility_mode -nocase -nowarn *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +set aclr_counter [get_collection_size $aclr_collection] +set clrn_counter [get_collection_size $clrn_collection] + +if {$aclr_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|aclr] +} + +if {$clrn_counter > 0} { + set_false_path -to [get_pins -compatibility_mode -nocase *|alt_rst_sync_uq1|altera_reset_synchronizer_int_chain*|clrn] +} diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.v b/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.v new file mode 100644 index 0000000..871cabe --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_controller.v @@ -0,0 +1,319 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// (C) 2001-2013 Altera Corporation. All rights reserved. +// Your use of Altera Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License Subscription +// Agreement, Altera MegaCore Function License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/21.1std/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $ +// $Revision: #1 $ +// $Date: 2020/06/22 $ +// $Author: psgswbuild $ + +// -------------------------------------- +// Reset controller +// +// Combines all the input resets and synchronizes +// the result to the clk. +// ACDS13.1 - Added reset request as part of reset sequencing +// -------------------------------------- + +`timescale 1 ns / 1 ns + +module altera_reset_controller +#( + parameter NUM_RESET_INPUTS = 6, + parameter USE_RESET_REQUEST_IN0 = 0, + parameter USE_RESET_REQUEST_IN1 = 0, + parameter USE_RESET_REQUEST_IN2 = 0, + parameter USE_RESET_REQUEST_IN3 = 0, + parameter USE_RESET_REQUEST_IN4 = 0, + parameter USE_RESET_REQUEST_IN5 = 0, + parameter USE_RESET_REQUEST_IN6 = 0, + parameter USE_RESET_REQUEST_IN7 = 0, + parameter USE_RESET_REQUEST_IN8 = 0, + parameter USE_RESET_REQUEST_IN9 = 0, + parameter USE_RESET_REQUEST_IN10 = 0, + parameter USE_RESET_REQUEST_IN11 = 0, + parameter USE_RESET_REQUEST_IN12 = 0, + parameter USE_RESET_REQUEST_IN13 = 0, + parameter USE_RESET_REQUEST_IN14 = 0, + parameter USE_RESET_REQUEST_IN15 = 0, + parameter OUTPUT_RESET_SYNC_EDGES = "deassert", + parameter SYNC_DEPTH = 2, + parameter RESET_REQUEST_PRESENT = 0, + parameter RESET_REQ_WAIT_TIME = 3, + parameter MIN_RST_ASSERTION_TIME = 11, + parameter RESET_REQ_EARLY_DSRT_TIME = 4, + parameter ADAPT_RESET_REQUEST = 0 +) +( + // -------------------------------------- + // We support up to 16 reset inputs, for now + // -------------------------------------- + input reset_in0, + input reset_in1, + input reset_in2, + input reset_in3, + input reset_in4, + input reset_in5, + input reset_in6, + input reset_in7, + input reset_in8, + input reset_in9, + input reset_in10, + input reset_in11, + input reset_in12, + input reset_in13, + input reset_in14, + input reset_in15, + input reset_req_in0, + input reset_req_in1, + input reset_req_in2, + input reset_req_in3, + input reset_req_in4, + input reset_req_in5, + input reset_req_in6, + input reset_req_in7, + input reset_req_in8, + input reset_req_in9, + input reset_req_in10, + input reset_req_in11, + input reset_req_in12, + input reset_req_in13, + input reset_req_in14, + input reset_req_in15, + + + input clk, + output reg reset_out, + output reg reset_req +); + + // Always use async reset synchronizer if reset_req is used + localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert"); + + // -------------------------------------- + // Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1 + // -------------------------------------- + localparam MIN_METASTABLE = 3; + localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME; + + localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME; + + localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ? + MIN_RST_ASSERTION_TIME + 1 : + ( + (MIN_RST_ASSERTION_TIME > LARGER)? + MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 : + MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2 + ); + + localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1; + // -------------------------------------- + + wire merged_reset; + wire merged_reset_req_in; + wire reset_out_pre; + wire reset_req_pre; + + // Registers and Interconnect + (*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain; + reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain; + reg r_sync_rst; + reg r_early_rst; + + // -------------------------------------- + // "Or" all the input resets together + // -------------------------------------- + assign merged_reset = ( + reset_in0 | + reset_in1 | + reset_in2 | + reset_in3 | + reset_in4 | + reset_in5 | + reset_in6 | + reset_in7 | + reset_in8 | + reset_in9 | + reset_in10 | + reset_in11 | + reset_in12 | + reset_in13 | + reset_in14 | + reset_in15 + ); + + assign merged_reset_req_in = ( + ( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) | + ( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) | + ( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) | + ( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) | + ( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) | + ( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) | + ( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) | + ( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) | + ( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) | + ( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) | + ( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) | + ( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) | + ( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) | + ( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) | + ( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) | + ( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0) + ); + + + // -------------------------------------- + // And if required, synchronize it to the required clock domain, + // with the correct synchronization type + // -------------------------------------- + generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin + + assign reset_out_pre = merged_reset; + assign reset_req_pre = merged_reset_req_in; + + end else begin + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET) + ) + alt_rst_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset), + .reset_out (reset_out_pre) + ); + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH), + .ASYNC_RESET(0) + ) + alt_rst_req_sync_uq1 + ( + .clk (clk), + .reset_in (merged_reset_req_in), + .reset_out (reset_req_pre) + ); + + end + endgenerate + + generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )| + ( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin + always @* begin + reset_out = reset_out_pre; + reset_req = reset_req_pre; + end + end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin + + wire reset_out_pre2; + + altera_reset_synchronizer + #( + .DEPTH (SYNC_DEPTH+1), + .ASYNC_RESET(0) + ) + alt_rst_sync_uq2 + ( + .clk (clk), + .reset_in (reset_out_pre), + .reset_out (reset_out_pre2) + ); + + always @* begin + reset_out = reset_out_pre2; + reset_req = reset_req_pre; + end + + end + else begin + + // 3-FF Metastability Synchronizer + initial + begin + altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}}; + end + + always @(posedge clk) + begin + altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <= + {altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre}; + end + + // Synchronous reset pipe + initial + begin + r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; + end + + always @(posedge clk) + begin + if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1) + begin + r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}}; + end + else + begin + r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]}; + end + end + + // Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition + // matches the early input. + + always @(posedge clk) + begin + case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst}) + 3'b000: r_sync_rst <= 1'b0; // Not reset + 3'b001: r_sync_rst <= 1'b0; + 3'b010: r_sync_rst <= 1'b0; + 3'b011: r_sync_rst <= 1'b1; + 3'b100: r_sync_rst <= 1'b1; + 3'b101: r_sync_rst <= 1'b1; + 3'b110: r_sync_rst <= 1'b1; + 3'b111: r_sync_rst <= 1'b1; // In Reset + default: r_sync_rst <= 1'b1; + endcase + + case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre}) + 2'b00: r_early_rst <= 1'b0; // Not reset + 2'b01: r_early_rst <= 1'b1; // Coming out of reset + 2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design. + 2'b11: r_early_rst <= 1'b1; // Held in reset + default: r_early_rst <= 1'b1; + endcase + end + + always @* begin + reset_out = r_sync_rst; + reset_req = r_early_rst; + end + + end + endgenerate + +endmodule diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v b/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v new file mode 100644 index 0000000..07e2443 --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/altera_reset_synchronizer.v @@ -0,0 +1,87 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// $Id: //acds/rel/21.1std/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $ +// $Revision: #1 $ +// $Date: 2020/06/22 $ +// $Author: psgswbuild $ + +// ----------------------------------------------- +// Reset Synchronizer +// ----------------------------------------------- +`timescale 1 ns / 1 ns + +module altera_reset_synchronizer +#( + parameter ASYNC_RESET = 1, + parameter DEPTH = 2 +) +( + input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */, + + input clk, + output reset_out +); + + // ----------------------------------------------- + // Synchronizer register chain. We cannot reuse the + // standard synchronizer in this implementation + // because our timing constraints are different. + // + // Instead of cutting the timing path to the d-input + // on the first flop we need to cut the aclr input. + // + // We omit the "preserve" attribute on the final + // output register, so that the synthesis tool can + // duplicate it where needed. + // ----------------------------------------------- + (*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain; + reg altera_reset_synchronizer_int_chain_out; + + generate if (ASYNC_RESET) begin + + // ----------------------------------------------- + // Assert asynchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk or posedge reset_in) begin + if (reset_in) begin + altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}}; + altera_reset_synchronizer_int_chain_out <= 1'b1; + end + else begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= 0; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end else begin + + // ----------------------------------------------- + // Assert synchronously, deassert synchronously. + // ----------------------------------------------- + always @(posedge clk) begin + altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1]; + altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in; + altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0]; + end + + assign reset_out = altera_reset_synchronizer_int_chain_out; + + end + endgenerate + +endmodule + diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v new file mode 100644 index 0000000..d9bb0fb --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_counters.v @@ -0,0 +1,161 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module reads and writes data to the RS232 connectpr on Altera's * + * DE1 and DE2 Development and Education Boards. * + * * + ******************************************************************************/ + +module altera_up_rs232_counters ( + // Inputs + clk, + reset, + + reset_counters, + + // Bidirectionals + + // Outputs + baud_clock_rising_edge, + baud_clock_falling_edge, + all_bits_transmitted +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // BAUD COUNTER WIDTH +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // TOTAL DATA WIDTH + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input reset_counters; + +// Bidirectionals + +// Outputs +output reg baud_clock_rising_edge; +output reg baud_clock_falling_edge; +output reg all_bits_transmitted; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires + +// Internal Registers +reg [(CW-1):0] baud_counter; +reg [ 3: 0] bit_counter; + +// State Machine Registers + + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + baud_counter <= {CW{1'b0}}; + else if (reset_counters) + baud_counter <= {CW{1'b0}}; + else if (baud_counter == BAUD_TICK_COUNT) + baud_counter <= {CW{1'b0}}; + else + baud_counter <= baud_counter + 1; +end + +always @(posedge clk) +begin + if (reset) + baud_clock_rising_edge <= 1'b0; + else if (baud_counter == BAUD_TICK_COUNT) + baud_clock_rising_edge <= 1'b1; + else + baud_clock_rising_edge <= 1'b0; +end + +always @(posedge clk) +begin + if (reset) + baud_clock_falling_edge <= 1'b0; + else if (baud_counter == HALF_BAUD_TICK_COUNT) + baud_clock_falling_edge <= 1'b1; + else + baud_clock_falling_edge <= 1'b0; +end + +always @(posedge clk) +begin + if (reset) + bit_counter <= 4'h0; + else if (reset_counters) + bit_counter <= 4'h0; + else if (bit_counter == TDW) + bit_counter <= 4'h0; + else if (baud_counter == BAUD_TICK_COUNT) + bit_counter <= bit_counter + 4'h1; +end + +always @(posedge clk) +begin + if (reset) + all_bits_transmitted <= 1'b0; + else if (bit_counter == TDW) + all_bits_transmitted <= 1'b1; + else + all_bits_transmitted <= 1'b0; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +endmodule + diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v new file mode 100644 index 0000000..ef294ef --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_in_deserializer.v @@ -0,0 +1,194 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module reads data to the RS232 UART Port. * + * * + ******************************************************************************/ + +module altera_up_rs232_in_deserializer ( + // Inputs + clk, + reset, + + serial_data_in, + + receive_data_en, + + // Bidirectionals + + // Outputs + fifo_read_available, + + received_data_valid, + received_data +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // Baud counter width +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // Total data width +parameter DW = 9; // Data width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input serial_data_in; + +input receive_data_en; + +// Bidirectionals + +// Outputs +output reg [ 7: 0] fifo_read_available; + +output received_data_valid; +output [DW: 0] received_data; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire shift_data_reg_en; +wire all_bits_received; + +wire fifo_is_empty; +wire fifo_is_full; +wire [ 6: 0] fifo_used; + +// Internal Registers +reg receiving_data; + +reg [(TDW-1):0] data_in_shift_reg; + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + fifo_read_available <= 8'h00; + else + fifo_read_available <= {fifo_is_full, fifo_used}; +end + +always @(posedge clk) +begin + if (reset) + receiving_data <= 1'b0; + else if (all_bits_received) + receiving_data <= 1'b0; + else if (serial_data_in == 1'b0) + receiving_data <= 1'b1; +end + +always @(posedge clk) +begin + if (reset) + data_in_shift_reg <= {TDW{1'b0}}; + else if (shift_data_reg_en) + data_in_shift_reg <= + {serial_data_in, data_in_shift_reg[(TDW - 1):1]}; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +// Output assignments +assign received_data_valid = ~fifo_is_empty; + +// Input assignments + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_counters RS232_In_Counters ( + // Inputs + .clk (clk), + .reset (reset), + + .reset_counters (~receiving_data), + + // Bidirectionals + + // Outputs + .baud_clock_rising_edge (), + .baud_clock_falling_edge (shift_data_reg_en), + .all_bits_transmitted (all_bits_received) +); +defparam + RS232_In_Counters.CW = CW, + RS232_In_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_In_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_In_Counters.TDW = TDW; + +altera_up_sync_fifo RS232_In_FIFO ( + // Inputs + .clk (clk), + .reset (reset), + + .write_en (all_bits_received & ~fifo_is_full), + .write_data (data_in_shift_reg[(DW + 1):1]), + + .read_en (receive_data_en & ~fifo_is_empty), + + // Bidirectionals + + // Outputs + .fifo_is_empty (fifo_is_empty), + .fifo_is_full (fifo_is_full), + .words_used (fifo_used), + + .read_data (received_data) +); +defparam + RS232_In_FIFO.DW = DW, + RS232_In_FIFO.DATA_DEPTH = 128, + RS232_In_FIFO.AW = 6; + +endmodule + diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v new file mode 100644 index 0000000..12250bf --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_rs232_out_serializer.v @@ -0,0 +1,202 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module writes data to the RS232 UART Port. * + * * + ******************************************************************************/ + +module altera_up_rs232_out_serializer ( + // Inputs + clk, + reset, + + transmit_data, + transmit_data_en, + + // Bidirectionals + + // Outputs + fifo_write_space, + + serial_data_out +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // Baud counter width +parameter BAUD_TICK_COUNT = 433; +parameter HALF_BAUD_TICK_COUNT = 216; + +parameter TDW = 11; // Total data width +parameter DW = 9; // Data width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input [DW: 0] transmit_data; +input transmit_data_en; + +// Bidirectionals + +// Outputs +output reg [ 7: 0] fifo_write_space; + +output reg serial_data_out; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire shift_data_reg_en; +wire all_bits_transmitted; + +wire read_fifo_en; + +wire fifo_is_empty; +wire fifo_is_full; +wire [ 6: 0] fifo_used; + +wire [DW: 0] data_from_fifo; + +// Internal Registers +reg transmitting_data; + +reg [DW+1:0] data_out_shift_reg; + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +always @(posedge clk) +begin + if (reset) + fifo_write_space <= 8'h00; + else + fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used}; +end + + +always @(posedge clk) +begin + if (reset) + serial_data_out <= 1'b1; + else + serial_data_out <= data_out_shift_reg[0]; +end + +always @(posedge clk) +begin + if (reset) + transmitting_data <= 1'b0; + else if (all_bits_transmitted) + transmitting_data <= 1'b0; + else if (fifo_is_empty == 1'b0) + transmitting_data <= 1'b1; +end + +always @(posedge clk) +begin + if (reset) + data_out_shift_reg <= {(DW + 2){1'b1}}; + else if (read_fifo_en) + data_out_shift_reg <= {data_from_fifo, 1'b0}; + else if (shift_data_reg_en) + data_out_shift_reg <= + {1'b1, data_out_shift_reg[DW+1:1]}; +end + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +assign read_fifo_en = + ~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted; + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_counters RS232_Out_Counters ( + // Inputs + .clk (clk), + .reset (reset), + + .reset_counters (~transmitting_data), + + // Bidirectionals + + // Outputs + .baud_clock_rising_edge (shift_data_reg_en), + .baud_clock_falling_edge (), + .all_bits_transmitted (all_bits_transmitted) +); +defparam + RS232_Out_Counters.CW = CW, + RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_Out_Counters.TDW = TDW; + +altera_up_sync_fifo RS232_Out_FIFO ( + // Inputs + .clk (clk), + .reset (reset), + + .write_en (transmit_data_en & ~fifo_is_full), + .write_data (transmit_data), + + .read_en (read_fifo_en), + + // Bidirectionals + + // Outputs + .fifo_is_empty (fifo_is_empty), + .fifo_is_full (fifo_is_full), + .words_used (fifo_used), + + .read_data (data_from_fifo) +); +defparam + RS232_Out_FIFO.DW = DW, + RS232_Out_FIFO.DATA_DEPTH = 128, + RS232_Out_FIFO.AW = 6; + +endmodule + diff --git a/Quartus/Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v new file mode 100644 index 0000000..6ed843f --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/altera_up_sync_fifo.v @@ -0,0 +1,152 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module is a FIFO with same clock for both reads and writes. * + * * + ******************************************************************************/ + +module altera_up_sync_fifo ( + // Inputs + clk, + reset, + + write_en, + write_data, + + read_en, + + // Bidirectionals + + // Outputs + fifo_is_empty, + fifo_is_full, + words_used, + + read_data +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter DW = 31; // Data width +parameter DATA_DEPTH = 128; +parameter AW = 6; // Address width + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ + +// Inputs +input clk; +input reset; + +input write_en; +input [DW: 0] write_data; + +input read_en; + +// Bidirectionals + +// Outputs +output fifo_is_empty; +output fifo_is_full; +output [AW: 0] words_used; + +output [DW: 0] read_data; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires + +// Internal Registers + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + + +scfifo Sync_FIFO ( + // Inputs + .clock (clk), + .sclr (reset), + + .data (write_data), + .wrreq (write_en), + + .rdreq (read_en), + + // Bidirectionals + + // Outputs + .empty (fifo_is_empty), + .full (fifo_is_full), + .usedw (words_used), + + .q (read_data) + + // Unused + // synopsys translate_off + , + .aclr (), + .almost_empty (), + .almost_full () + // synopsys translate_on +); +defparam + Sync_FIFO.add_ram_output_register = "OFF", + Sync_FIFO.intended_device_family = "Cyclone II", + Sync_FIFO.lpm_numwords = DATA_DEPTH, + Sync_FIFO.lpm_showahead = "ON", + Sync_FIFO.lpm_type = "scfifo", + Sync_FIFO.lpm_width = DW + 1, + Sync_FIFO.lpm_widthu = AW + 1, + Sync_FIFO.overflow_checking = "OFF", + Sync_FIFO.underflow_checking = "OFF", + Sync_FIFO.use_eab = "ON"; + +endmodule + diff --git a/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v b/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v new file mode 100644 index 0000000..702bbdf --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/submodules/uart_screen_rs232_0.v @@ -0,0 +1,187 @@ +// (C) 2001-2021 Intel Corporation. All rights reserved. +// Your use of Intel Corporation's design tools, logic functions and other +// software and tools, and its AMPP partner logic functions, and any output +// files from any of the foregoing (including device programming or simulation +// files), and any associated documentation or information are expressly subject +// to the terms and conditions of the Intel Program License Subscription +// Agreement, Intel FPGA IP License Agreement, or other applicable +// license agreement, including, without limitation, that your use is for the +// sole purpose of programming logic devices manufactured by Intel and sold by +// Intel or its authorized distributors. Please refer to the applicable +// agreement for further details. + + +// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS +// IN THIS FILE. + +/****************************************************************************** + * * + * This module reads and writes data to the RS232 connector on Altera's * + * DE-series Development and Education Boards. * + * * + ******************************************************************************/ + +module uart_screen_rs232_0 ( + // Inputs + clk, + reset, + + from_uart_ready, + + to_uart_data, + to_uart_error, + to_uart_valid, + + UART_RXD, + + // Bidirectionals + + // Outputs + from_uart_data, + from_uart_error, + from_uart_valid, + + to_uart_ready, + + UART_TXD +); + +/***************************************************************************** + * Parameter Declarations * + *****************************************************************************/ + +parameter CW = 9; // Baud counter width +parameter BAUD_TICK_COUNT = 434; +parameter HALF_BAUD_TICK_COUNT = 217; + +parameter TDW = 10; // Total data width +parameter DW = 8; // Data width +parameter ODD_PARITY = 1'b0; + +/***************************************************************************** + * Port Declarations * + *****************************************************************************/ +// Inputs +input clk; +input reset; + +input from_uart_ready; + +input [(DW-1):0] to_uart_data; +input to_uart_error; +input to_uart_valid; + +input UART_RXD; + +// Bidirectionals + +// Outputs +output [(DW-1):0] from_uart_data; +output from_uart_error; +output from_uart_valid; + +output to_uart_ready; + +output UART_TXD; + +/***************************************************************************** + * Constant Declarations * + *****************************************************************************/ + +/***************************************************************************** + * Internal Wires and Registers Declarations * + *****************************************************************************/ + +// Internal Wires +wire [(DW-1):0] read_data; + +wire write_data_parity; +wire [ 7: 0] write_space; + +// Internal Registers + +// State Machine Registers + +/***************************************************************************** + * Finite State Machine(s) * + *****************************************************************************/ + + +/***************************************************************************** + * Sequential Logic * + *****************************************************************************/ + +// Output Registers + +// Internal Registers + +/***************************************************************************** + * Combinational Logic * + *****************************************************************************/ + +// Output Assignments +assign from_uart_data = read_data; +assign from_uart_error = 1'b0; + +assign to_uart_ready = (|(write_space)); + +// Internal Assignments +assign write_data_parity = (^(to_uart_data)) ^ ODD_PARITY; + +/***************************************************************************** + * Internal Modules * + *****************************************************************************/ + +altera_up_rs232_in_deserializer RS232_In_Deserializer ( + // Inputs + .clk (clk), + .reset (reset), + + .serial_data_in (UART_RXD), + + .receive_data_en (from_uart_ready), + + // Bidirectionals + + // Outputs + .fifo_read_available (), + + .received_data_valid (from_uart_valid), + .received_data (read_data) +); +defparam + RS232_In_Deserializer.CW = CW, + RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_In_Deserializer.TDW = TDW, + RS232_In_Deserializer.DW = (DW - 1); + +altera_up_rs232_out_serializer RS232_Out_Serializer ( + // Inputs + .clk (clk), + .reset (reset), + + .transmit_data (to_uart_data), + .transmit_data_en (to_uart_valid & to_uart_ready), + + // Bidirectionals + + // Outputs + .fifo_write_space (write_space), + + .serial_data_out (UART_TXD) +); +defparam + RS232_Out_Serializer.CW = CW, + RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT, + RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT, + RS232_Out_Serializer.TDW = TDW, + RS232_Out_Serializer.DW = (DW - 1); + +endmodule + diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo b/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo new file mode 100644 index 0000000..51c0b8b --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/uart_screen.debuginfo @@ -0,0 +1,1614 @@ + + + + + + + com.altera.sopcmodel.ensemble.EClockAdapter + HANDSHAKE + false + true + true + true + + + java.lang.String + EP4CE6E22C8 + false + true + true + true + + + java.lang.String + CYCLONEIVE + false + true + true + true + + + java.lang.String + 8 + false + true + false + true + + + com.altera.sopcmodel.ensemble.Ensemble$EFabricMode + QSYS + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1653392990 + false + true + true + true + + + boolean + false + false + true + false + true + + + com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage + VERILOG + false + false + false + true + + + boolean + true + false + true + true + true + + + com.altera.sopcmodel.definition.BoundaryDefinition + + false + true + false + true + + + int + 1 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + boolean + false + false + true + false + true + + + long + 0 + false + true + false + true + + + java.lang.String + + false + true + false + true + + + long + 0 + false + true + false + true + + + boolean + false + false + true + false + true + + + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + long + 0 + false + true + false + true + CLOCK_RATE + clk_in + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + qsys.ui.export_name + clk + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + in_clk + Input + 1 + clk + + + + + + qsys.ui.export_name + reset + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_n + Input + 1 + reset_n + + + + + + java.lang.String + clk_in + false + true + true + true + + + long + 50000000 + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + true + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + true + + clk_out + Output + 1 + clk + + + false + rs232_0 + clk + rs232_0.clk + + + false + rst_controller + clk + rst_controller.clk + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + clk_in_reset + false + true + true + true + + + [Ljava.lang.String; + clk_in_reset + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_n_out + Output + 1 + reset_n + + + + + + + double + 5.0E7 + true + false + false + true + + + java.lang.String + Streaming + false + true + true + true + + + int + 115200 + false + true + true + true + + + java.lang.String + None + false + true + true + true + + + int + 8 + false + true + true + true + + + int + 1 + false + true + true + true + + + java.lang.String + CYCLONEIVE + false + true + false + true + DEVICE_FAMILY + + + java.lang.Long + 50000000 + false + true + false + true + CLOCK_RATE + clk + + + java.lang.String + Cyclone IV E + false + true + false + true + DEVICE_FAMILY + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.Boolean + true + true + true + false + true + + + java.lang.Long + 50000000 + true + true + false + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + true + + from_uart_ready + Input + 1 + ready + + + from_uart_data + Output + 8 + data + + + from_uart_error + Output + 1 + error + + + from_uart_valid + Output + 1 + valid + + + + + + java.lang.String + clk + false + true + false + true + + + java.lang.String + reset + false + true + false + true + + + int + 1 + false + true + false + true + + + int + 8 + false + true + true + true + + + boolean + false + false + true + false + true + + + [Ljava.lang.String; + + false + true + true + true + + + boolean + true + false + true + true + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon_streaming + false + + to_uart_data + Input + 8 + data + + + to_uart_error + Input + 1 + error + + + to_uart_valid + Input + 1 + valid + + + to_uart_ready + Output + 1 + ready + + + + + + java.lang.String + + false + true + true + true + + + java.lang.String + + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + conduit + false + + UART_RXD + Input + 1 + export + + + UART_TXD + Output + 1 + export + + + + + + + int + 1 + false + true + true + true + + + java.lang.String + deassert + false + true + true + true + + + int + 2 + false + true + true + true + + + int + 0 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 3 + false + true + true + true + + + int + 1 + false + true + true + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + int + 0 + true + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + java.lang.String + + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + NONE + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset_in0 + Input + 1 + reset + + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk + false + true + true + true + + + java.lang.String + + false + true + true + true + + + [Ljava.lang.String; + reset_in0 + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + true + + reset_out + Output + 1 + reset + + + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + rs232_0 + clk + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + rst_controller + reset_out + rs232_0 + reset + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk_reset + rst_controller + reset_in0 + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_0 + clk + rst_controller + clk + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Clock Source + 21.1 + + + 1 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 1 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + clock_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Output + 21.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 21.1 + + + 1 + altera_up_avalon_rs232 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + RS232 UART + 17.1 + + + 2 + clock_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Clock Input + 21.1 + + + 2 + reset_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Input + 21.1 + + + 1 + avalon_streaming_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Source + 21.1 + + + 1 + avalon_streaming_sink + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Avalon Streaming Sink + 21.1 + + + 1 + conduit_end + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Conduit + 21.1 + + + 1 + altera_reset_controller + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + Merlin Reset Controller + 21.1 + + + 1 + reset_source + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IMutableConnectionPoint + Reset Output + 21.1 + + + 1 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 21.1 + + + 2 + reset + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Reset Connection + 21.1 + + + 1 + clock + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IConnection + Clock Connection + 21.1 + + 21.1 842 + CCD9AC02D57D00000180F5E6E111 + diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.qip b/Quartus/Design/uart_screen/synthesis/uart_screen.qip new file mode 100644 index 0000000..0b6225e --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/uart_screen.qip @@ -0,0 +1,84 @@ +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_NAME "Qsys" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TOOL_ENV "Qsys" +set_global_assignment -library "uart_screen" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../uart_screen.sopcinfo"] +set_global_assignment -entity "uart_screen" -library "uart_screen" -name SLD_INFO "QSYS_NAME uart_screen HAS_SOPCINFO 1 GENERATION_ID 1653392990" +set_global_assignment -library "uart_screen" -name MISC_FILE [file join $::quartus(qip_path) "../uart_screen.cmp"] +set_global_assignment -library "uart_screen" -name SLD_FILE [file join $::quartus(qip_path) "uart_screen.debuginfo"] +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_TARGETED_DEVICE_FAMILY "Cyclone IV E" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_QSYS_MODE "SYSTEM" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -library "uart_screen" -name MISC_FILE [file join $::quartus(qip_path) "../../uart_screen.qsys"] +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_NAME "dWFydF9zY3JlZW4=" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_DISPLAY_NAME "dWFydF9zY3JlZW4=" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "On" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_VERSION "MS4w" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTY1MzM5Mjk5MA==::QXV0byBHRU5FUkFUSU9OX0lE" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::RVA0Q0U2RTIyQzg=::QXV0byBERVZJQ0U=" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ==" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfRE9NQUlO::LTE=::QXV0byBDTE9DS19ET01BSU4=" +set_global_assignment -entity "uart_screen" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfUkVTRVRfRE9NQUlO::LTE=::QXV0byBSRVNFVF9ET01BSU4=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_NAME "YWx0ZXJhX3Jlc2V0X2NvbnRyb2xsZXI=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_DISPLAY_NAME "TWVybGluIFJlc2V0IENvbnRyb2xsZXI=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_VERSION "MjEuMQ==" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_DESCRIPTION "Rm9yIHN5c3RlbXMgd2l0aCBtdWx0aXBsZSByZXNldCBpbnB1dHMsIHRoZSBNZXJsaW4gUmVzZXQgQ29udHJvbGxlciBPUnMgYWxsIHJlc2V0IGlucHV0cyBhbmQgZ2VuZXJhdGVzIGEgc2luZ2xlIHJlc2V0IG91dHB1dC4=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "TlVNX1JFU0VUX0lOUFVUUw==::MQ==::TnVtYmVyIG9mIGlucHV0cw==" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "T1VUUFVUX1JFU0VUX1NZTkNfRURHRVM=::ZGVhc3NlcnQ=::T3V0cHV0IFJlc2V0IFN5bmNocm9ub3VzIEVkZ2Vz" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "U1lOQ19ERVBUSA==::Mg==::U3luY2hyb25pemVyIGRlcHRo" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRVUVTVF9QUkVTRU5U::MA==::UmVzZXQgcmVxdWVzdCBsb2dpYyBlbmFibGU=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX1dBSVRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCB3YWl0IHRpbWU=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "TUlOX1JTVF9BU1NFUlRJT05fVElNRQ==::Mw==::TWluaW11bSByZXNldCBhc3NlcnRpb24gdGltZQ==" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "UkVTRVRfUkVRX0VBUkxZX0RTUlRfVElNRQ==::MQ==::UmVzZXQgcmVxdWVzdCBkZWFzc2VydCB0aW1pbmc=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4w::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjA=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4x::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4y::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjI=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4z::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjM=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU40::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjQ=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU41::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjU=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU42::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjY=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU43::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjc=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU44::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjg=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU45::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjk=" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEw" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEx" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMg==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEy" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xMw==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjEz" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNA==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE0" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU4xNQ==::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcG9ydCByZXNldF9pbjE1" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "VVNFX1JFU0VUX1JFUVVFU1RfSU5QVVQ=::MA==::RW5hYmxlIHJlc2V0X3JlcSBmb3IgcmVzZXRfaW5wdXRz" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QURBUFRfUkVTRVRfUkVRVUVTVA==::MA==::T25seSBhZGFwdCBvbmx5IHJlc2V0IHJlcXVlc3Q=" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_NAME "dWFydF9zY3JlZW5fcnMyMzJfMA==" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_DISPLAY_NAME "UlMyMzIgVUFSVA==" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_AUTHOR "SW50ZWwgRlBHQSBVbml2ZXJzaXR5IFByb2dyYW0=" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_VERSION "MTcuMQ==" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_DESCRIPTION "UlMyMzIgVUFSVCBDb250cm9sbGVy" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YXZhbG9uX2J1c190eXBl::U3RyZWFtaW5n::QXZhbG9uIFR5cGU=" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "YmF1ZA==::MTE1MjAw::QmF1ZCBSYXRlIChicHMp" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "cGFyaXR5::Tm9uZQ==::UGFyaXR5" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "ZGF0YV9iaXRz::OA==::RGF0YSBCaXRz" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "c3RvcF9iaXRz::MQ==::U3RvcCBCaXRz" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBJViBF::QXV0byBERVZJQ0VfRkFNSUxZ" +set_global_assignment -entity "uart_screen_rs232_0" -library "uart_screen" -name IP_COMPONENT_PARAMETER "QVVUT19DTEtfQ0xPQ0tfUkFURQ==::NTAwMDAwMDA=::QXV0byBDTE9DS19SQVRF" + +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "uart_screen.v"] +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.v"] +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_reset_synchronizer.v"] +set_global_assignment -library "uart_screen" -name SDC_FILE [file join $::quartus(qip_path) "submodules/altera_reset_controller.sdc"] +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_counters.v"] +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_in_deserializer.v"] +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_rs232_out_serializer.v"] +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/altera_up_sync_fifo.v"] +set_global_assignment -library "uart_screen" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/uart_screen_rs232_0.v"] + +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_TOOL_NAME "altera_reset_controller" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_TOOL_VERSION "21.1" +set_global_assignment -entity "altera_reset_controller" -library "uart_screen" -name IP_TOOL_ENV "Qsys" diff --git a/Quartus/Design/uart_screen/synthesis/uart_screen.v b/Quartus/Design/uart_screen/synthesis/uart_screen.v new file mode 100644 index 0000000..6b0e81e --- /dev/null +++ b/Quartus/Design/uart_screen/synthesis/uart_screen.v @@ -0,0 +1,101 @@ +// uart_screen.v + +// Generated using ACDS version 21.1 842 + +`timescale 1 ps / 1 ps +module uart_screen ( + input wire clk_clk, // clk.clk + input wire reset_reset_n, // reset.reset_n + input wire rs232_0_from_uart_ready, // rs232_0_avalon_data_receive_source.ready + output wire [7:0] rs232_0_from_uart_data, // .data + output wire rs232_0_from_uart_error, // .error + output wire rs232_0_from_uart_valid, // .valid + input wire [7:0] rs232_0_to_uart_data, // rs232_0_avalon_data_transmit_sink.data + input wire rs232_0_to_uart_error, // .error + input wire rs232_0_to_uart_valid, // .valid + output wire rs232_0_to_uart_ready, // .ready + input wire rs232_0_UART_RXD, // rs232_0_external_interface.RXD + output wire rs232_0_UART_TXD // .TXD + ); + + wire rst_controller_reset_out_reset; // rst_controller:reset_out -> rs232_0:reset + + uart_screen_rs232_0 rs232_0 ( + .clk (clk_clk), // clk.clk + .reset (rst_controller_reset_out_reset), // reset.reset + .from_uart_ready (rs232_0_from_uart_ready), // avalon_data_receive_source.ready + .from_uart_data (rs232_0_from_uart_data), // .data + .from_uart_error (rs232_0_from_uart_error), // .error + .from_uart_valid (rs232_0_from_uart_valid), // .valid + .to_uart_data (rs232_0_to_uart_data), // avalon_data_transmit_sink.data + .to_uart_error (rs232_0_to_uart_error), // .error + .to_uart_valid (rs232_0_to_uart_valid), // .valid + .to_uart_ready (rs232_0_to_uart_ready), // .ready + .UART_RXD (rs232_0_UART_RXD), // external_interface.export + .UART_TXD (rs232_0_UART_TXD) // .export + ); + + altera_reset_controller #( + .NUM_RESET_INPUTS (1), + .OUTPUT_RESET_SYNC_EDGES ("deassert"), + .SYNC_DEPTH (2), + .RESET_REQUEST_PRESENT (0), + .RESET_REQ_WAIT_TIME (1), + .MIN_RST_ASSERTION_TIME (3), + .RESET_REQ_EARLY_DSRT_TIME (1), + .USE_RESET_REQUEST_IN0 (0), + .USE_RESET_REQUEST_IN1 (0), + .USE_RESET_REQUEST_IN2 (0), + .USE_RESET_REQUEST_IN3 (0), + .USE_RESET_REQUEST_IN4 (0), + .USE_RESET_REQUEST_IN5 (0), + .USE_RESET_REQUEST_IN6 (0), + .USE_RESET_REQUEST_IN7 (0), + .USE_RESET_REQUEST_IN8 (0), + .USE_RESET_REQUEST_IN9 (0), + .USE_RESET_REQUEST_IN10 (0), + .USE_RESET_REQUEST_IN11 (0), + .USE_RESET_REQUEST_IN12 (0), + .USE_RESET_REQUEST_IN13 (0), + .USE_RESET_REQUEST_IN14 (0), + .USE_RESET_REQUEST_IN15 (0), + .ADAPT_RESET_REQUEST (0) + ) rst_controller ( + .reset_in0 (~reset_reset_n), // reset_in0.reset + .clk (clk_clk), // clk.clk + .reset_out (rst_controller_reset_out_reset), // reset_out.reset + .reset_req (), // (terminated) + .reset_req_in0 (1'b0), // (terminated) + .reset_in1 (1'b0), // (terminated) + .reset_req_in1 (1'b0), // (terminated) + .reset_in2 (1'b0), // (terminated) + .reset_req_in2 (1'b0), // (terminated) + .reset_in3 (1'b0), // (terminated) + .reset_req_in3 (1'b0), // (terminated) + .reset_in4 (1'b0), // (terminated) + .reset_req_in4 (1'b0), // (terminated) + .reset_in5 (1'b0), // (terminated) + .reset_req_in5 (1'b0), // (terminated) + .reset_in6 (1'b0), // (terminated) + .reset_req_in6 (1'b0), // (terminated) + .reset_in7 (1'b0), // (terminated) + .reset_req_in7 (1'b0), // (terminated) + .reset_in8 (1'b0), // (terminated) + .reset_req_in8 (1'b0), // (terminated) + .reset_in9 (1'b0), // (terminated) + .reset_req_in9 (1'b0), // (terminated) + .reset_in10 (1'b0), // (terminated) + .reset_req_in10 (1'b0), // (terminated) + .reset_in11 (1'b0), // (terminated) + .reset_req_in11 (1'b0), // (terminated) + .reset_in12 (1'b0), // (terminated) + .reset_req_in12 (1'b0), // (terminated) + .reset_in13 (1'b0), // (terminated) + .reset_req_in13 (1'b0), // (terminated) + .reset_in14 (1'b0), // (terminated) + .reset_req_in14 (1'b0), // (terminated) + .reset_in15 (1'b0), // (terminated) + .reset_req_in15 (1'b0) // (terminated) + ); + +endmodule diff --git a/Quartus/Design/uart_screen/uart_screen.bsf b/Quartus/Design/uart_screen/uart_screen.bsf new file mode 100644 index 0000000..98e4a45 --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen.bsf @@ -0,0 +1,149 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2021 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 544 288) + (text "uart_screen" (rect 237 -1 285 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 272 20 284)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "clk_clk" (rect 0 0 27 12)(font "Arial" (font_size 8))) + (text "clk_clk" (rect 4 61 46 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 224 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "reset_reset_n" (rect 0 0 56 12)(font "Arial" (font_size 8))) + (text "reset_reset_n" (rect 4 101 82 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 224 112)(line_width 1)) + ) + (port + (pt 544 72) + (input) + (text "rs232_0_from_uart_ready" (rect 0 0 109 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_ready" (rect 410 61 548 72)(font "Arial" (font_size 8))) + (line (pt 544 72)(pt 304 72)(line_width 1)) + ) + (port + (pt 0 152) + (input) + (text "rs232_0_to_uart_data[7..0]" (rect 0 0 109 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_data[7..0]" (rect 4 141 160 152)(font "Arial" (font_size 8))) + (line (pt 0 152)(pt 224 152)(line_width 3)) + ) + (port + (pt 0 168) + (input) + (text "rs232_0_to_uart_error" (rect 0 0 93 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_error" (rect 4 157 130 168)(font "Arial" (font_size 8))) + (line (pt 0 168)(pt 224 168)(line_width 1)) + ) + (port + (pt 0 184) + (input) + (text "rs232_0_to_uart_valid" (rect 0 0 90 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_valid" (rect 4 173 130 184)(font "Arial" (font_size 8))) + (line (pt 0 184)(pt 224 184)(line_width 1)) + ) + (port + (pt 0 240) + (input) + (text "rs232_0_UART_RXD" (rect 0 0 95 12)(font "Arial" (font_size 8))) + (text "rs232_0_UART_RXD" (rect 4 229 100 240)(font "Arial" (font_size 8))) + (line (pt 0 240)(pt 224 240)(line_width 1)) + ) + (port + (pt 544 88) + (output) + (text "rs232_0_from_uart_data[7..0]" (rect 0 0 122 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_data[7..0]" (rect 393 77 561 88)(font "Arial" (font_size 8))) + (line (pt 544 88)(pt 304 88)(line_width 3)) + ) + (port + (pt 544 104) + (output) + (text "rs232_0_from_uart_error" (rect 0 0 106 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_error" (rect 414 93 552 104)(font "Arial" (font_size 8))) + (line (pt 544 104)(pt 304 104)(line_width 1)) + ) + (port + (pt 544 120) + (output) + (text "rs232_0_from_uart_valid" (rect 0 0 103 12)(font "Arial" (font_size 8))) + (text "rs232_0_from_uart_valid" (rect 416 109 554 120)(font "Arial" (font_size 8))) + (line (pt 544 120)(pt 304 120)(line_width 1)) + ) + (port + (pt 0 200) + (output) + (text "rs232_0_to_uart_ready" (rect 0 0 96 12)(font "Arial" (font_size 8))) + (text "rs232_0_to_uart_ready" (rect 4 189 130 200)(font "Arial" (font_size 8))) + (line (pt 0 200)(pt 224 200)(line_width 1)) + ) + (port + (pt 0 256) + (output) + (text "rs232_0_UART_TXD" (rect 0 0 93 12)(font "Arial" (font_size 8))) + (text "rs232_0_UART_TXD" (rect 4 245 100 256)(font "Arial" (font_size 8))) + (line (pt 0 256)(pt 224 256)(line_width 1)) + ) + (drawing + (text "clk" (rect 209 43 436 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 229 67 476 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 195 83 420 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset_n" (rect 229 107 500 224)(font "Arial" (color 0 0 0))) + (text "rs232_0_avalon_data_receive_source" (rect 305 43 814 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "ready" (rect 276 67 582 144)(font "Arial" (color 0 0 0))) + (text "data" (rect 283 83 590 176)(font "Arial" (color 0 0 0))) + (text "error" (rect 279 99 588 208)(font "Arial" (color 0 0 0))) + (text "valid" (rect 281 115 592 240)(font "Arial" (color 0 0 0))) + (text "rs232_0_avalon_data_transmit_sink" (rect 11 123 220 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "data" (rect 229 147 482 304)(font "Arial" (color 0 0 0))) + (text "error" (rect 229 163 488 336)(font "Arial" (color 0 0 0))) + (text "valid" (rect 229 179 488 368)(font "Arial" (color 0 0 0))) + (text "ready" (rect 229 195 488 400)(font "Arial" (color 0 0 0))) + (text "rs232_0_external_interface" (rect 64 211 284 435)(font "Arial" (color 128 0 0)(font_size 9))) + (text "RXD" (rect 229 235 476 480)(font "Arial" (color 0 0 0))) + (text "TXD" (rect 229 251 476 512)(font "Arial" (color 0 0 0))) + (text " uart_screen " (rect 489 272 1056 554)(font "Arial" )) + (line (pt 224 32)(pt 304 32)(line_width 1)) + (line (pt 304 32)(pt 304 272)(line_width 1)) + (line (pt 224 272)(pt 304 272)(line_width 1)) + (line (pt 224 32)(pt 224 272)(line_width 1)) + (line (pt 225 52)(pt 225 76)(line_width 1)) + (line (pt 226 52)(pt 226 76)(line_width 1)) + (line (pt 225 92)(pt 225 116)(line_width 1)) + (line (pt 226 92)(pt 226 116)(line_width 1)) + (line (pt 303 52)(pt 303 124)(line_width 1)) + (line (pt 302 52)(pt 302 124)(line_width 1)) + (line (pt 225 132)(pt 225 204)(line_width 1)) + (line (pt 226 132)(pt 226 204)(line_width 1)) + (line (pt 225 220)(pt 225 260)(line_width 1)) + (line (pt 226 220)(pt 226 260)(line_width 1)) + (line (pt 0 0)(pt 544 0)(line_width 1)) + (line (pt 544 0)(pt 544 288)(line_width 1)) + (line (pt 0 288)(pt 544 288)(line_width 1)) + (line (pt 0 0)(pt 0 288)(line_width 1)) + ) +) diff --git a/Quartus/Design/uart_screen/uart_screen.cmp b/Quartus/Design/uart_screen/uart_screen.cmp new file mode 100644 index 0000000..f83bb30 --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen.cmp @@ -0,0 +1,17 @@ + component uart_screen is + port ( + clk_clk : in std_logic := 'X'; -- clk + reset_reset_n : in std_logic := 'X'; -- reset_n + rs232_0_from_uart_ready : in std_logic := 'X'; -- ready + rs232_0_from_uart_data : out std_logic_vector(7 downto 0); -- data + rs232_0_from_uart_error : out std_logic; -- error + rs232_0_from_uart_valid : out std_logic; -- valid + rs232_0_to_uart_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data + rs232_0_to_uart_error : in std_logic := 'X'; -- error + rs232_0_to_uart_valid : in std_logic := 'X'; -- valid + rs232_0_to_uart_ready : out std_logic; -- ready + rs232_0_UART_RXD : in std_logic := 'X'; -- RXD + rs232_0_UART_TXD : out std_logic -- TXD + ); + end component uart_screen; + diff --git a/Quartus/Design/uart_screen/uart_screen.html b/Quartus/Design/uart_screen/uart_screen.html new file mode 100644 index 0000000..eef457d --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen.html @@ -0,0 +1,236 @@ + + + + + datasheet for uart_screen + + + + + + + + +
uart_screen +
+
+
+ + + + + +
2022.05.24.19:49:50Datasheet
+
+
Overview
+
+
+ + + + + + + + +
  clk_0 uart_screen
+
+
+
+
+
+
+
Memory Map
+ + + + +
+ +
+
+

clk_0

clock_source v21.1 +
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + +
clockFrequency50000000
clockFrequencyKnowntrue
inputClockFrequency0
resetSynchronousEdgesNONE
deviceFamilyUNKNOWN
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ +
+
+

rs232_0

altera_up_avalon_rs232 v17.1 +
+
+ + + + + + + + + + + + + + + +
+ clk_0 + clk  rs232_0
  clk
clk_reset  
  reset
+
+
+
+ + + + +
+

Parameters

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ref_clk_freq5.0E7
avalon_bus_typeStreaming
baud115200
parityNone
data_bits8
stop_bits1
AUTO_DEVICE_FAMILYCYCLONEIVE
AUTO_CLK_CLOCK_RATE50000000
deviceFamilyCyclone IV E
generateLegacySimfalse
+
   + + + + +
+

Software Assignments

(none)
+
+ + + + + +
generation took 0.00 secondsrendering took 0.03 seconds
+ + diff --git a/Quartus/Design/uart_screen/uart_screen.ppf b/Quartus/Design/uart_screen/uart_screen.ppf new file mode 100644 index 0000000..75d49b3 --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen.ppf @@ -0,0 +1,21 @@ + + + + + + + + + + + + + + + + + diff --git a/Quartus/Design/uart_screen/uart_screen.xml b/Quartus/Design/uart_screen/uart_screen.xml new file mode 100644 index 0000000..f15ee80 --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen.xml @@ -0,0 +1,313 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 0 starting:uart_screen "uart_screen" + + + + Transform: CustomInstructionTransform + No custom instruction connections, skipping transform + 2 modules, 2 connections]]> + Transform: MMTransform + Transform: InterruptMapperTransform + Transform: InterruptSyncTransform + Transform: InterruptFanoutTransform + Transform: AvalonStreamingTransform + Transform: ResetAdaptation + + + + 3 modules, 4 connections]]> + uart_screen" reuses altera_up_avalon_rs232 "submodules/uart_screen_rs232_0"]]> + uart_screen" reuses altera_reset_controller "submodules/altera_reset_controller"]]> + queue size: 1 starting:altera_up_avalon_rs232 "submodules/uart_screen_rs232_0" + Starting Generation of RS232 UART + uart_screen" instantiated altera_up_avalon_rs232 "rs232_0"]]> + queue size: 0 starting:altera_reset_controller "submodules/altera_reset_controller" + uart_screen" instantiated altera_reset_controller "rst_controller"]]> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + queue size: 1 starting:altera_up_avalon_rs232 "submodules/uart_screen_rs232_0" + Starting Generation of RS232 UART + uart_screen" instantiated altera_up_avalon_rs232 "rs232_0"]]> + + + + + + + + + + + + + + + + queue size: 0 starting:altera_reset_controller "submodules/altera_reset_controller" + uart_screen" instantiated altera_reset_controller "rst_controller"]]> + + + diff --git a/Quartus/Design/uart_screen/uart_screen_bb.v b/Quartus/Design/uart_screen/uart_screen_bb.v new file mode 100644 index 0000000..5adf74c --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen_bb.v @@ -0,0 +1,28 @@ + +module uart_screen ( + rs232_0_UART_RXD, + rs232_0_UART_TXD, + rs232_0_from_uart_ready, + rs232_0_from_uart_data, + rs232_0_from_uart_error, + rs232_0_from_uart_valid, + rs232_0_to_uart_data, + rs232_0_to_uart_error, + rs232_0_to_uart_valid, + rs232_0_to_uart_ready, + clk_clk, + reset_reset_n); + + input rs232_0_UART_RXD; + output rs232_0_UART_TXD; + input rs232_0_from_uart_ready; + output [7:0] rs232_0_from_uart_data; + output rs232_0_from_uart_error; + output rs232_0_from_uart_valid; + input [7:0] rs232_0_to_uart_data; + input rs232_0_to_uart_error; + input rs232_0_to_uart_valid; + output rs232_0_to_uart_ready; + input clk_clk; + input reset_reset_n; +endmodule diff --git a/Quartus/Design/uart_screen/uart_screen_generation.rpt b/Quartus/Design/uart_screen/uart_screen_generation.rpt new file mode 100644 index 0000000..943e128 --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen_generation.rpt @@ -0,0 +1,34 @@ +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/uart_screen.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: qsys-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/uart_screen.qsys +Progress: Reading input file +Progress: Adding clk_0 [clock_source 21.1] +Progress: Parameterizing module clk_0 +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: uart_screen: Generating uart_screen "uart_screen" for QUARTUS_SYNTH +Info: rs232_0: Starting Generation of RS232 UART +Info: rs232_0: "uart_screen" instantiated altera_up_avalon_rs232 "rs232_0" +Info: rst_controller: "uart_screen" instantiated altera_reset_controller "rst_controller" +Info: uart_screen: Done "uart_screen" with 3 modules, 9 files +Info: qsys-generate succeeded. +Info: Finished: Create HDL design files for synthesis diff --git a/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt b/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt new file mode 100644 index 0000000..27df025 --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen_generation_previous.rpt @@ -0,0 +1,30 @@ +Info: Starting: Create block symbol file (.bsf) +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/uart_screen.qsys +Progress: Reading input file +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: qsys-generate succeeded. +Info: Finished: Create block symbol file (.bsf) +Info: +Info: Starting: Create HDL design files for synthesis +Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/uart_screen.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/uart_screen/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8 +Progress: Loading Design/uart_screen.qsys +Progress: Reading input file +Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1] +Progress: Parameterizing module rs232_0 +Progress: Building connections +Progress: Parameterizing connections +Progress: Validating +Progress: Done reading input file +Info: uart_screen: Generating uart_screen "uart_screen" for QUARTUS_SYNTH +Info: rs232_0: Starting Generation of RS232 UART +Error: rs232_0: The input clock frequency must be known at generation time. +Info: rs232_0: "uart_screen" instantiated altera_up_avalon_rs232 "rs232_0" +Info: uart_screen: Done "uart_screen" with 2 modules, 6 files +Error: qsys-generate failed with exit code 1: 1 Error, 0 Warnings +Info: Finished: Create HDL design files for synthesis diff --git a/Quartus/Design/uart_screen/uart_screen_inst.v b/Quartus/Design/uart_screen/uart_screen_inst.v new file mode 100644 index 0000000..3aa6c7c --- /dev/null +++ b/Quartus/Design/uart_screen/uart_screen_inst.v @@ -0,0 +1,15 @@ + uart_screen u0 ( + .rs232_0_UART_RXD (), // rs232_0_external_interface.RXD + .rs232_0_UART_TXD (), // .TXD + .rs232_0_from_uart_ready (), // rs232_0_avalon_data_receive_source.ready + .rs232_0_from_uart_data (), // .data + .rs232_0_from_uart_error (), // .error + .rs232_0_from_uart_valid (), // .valid + .rs232_0_to_uart_data (), // rs232_0_avalon_data_transmit_sink.data + .rs232_0_to_uart_error (), // .error + .rs232_0_to_uart_valid (), // .valid + .rs232_0_to_uart_ready (), // .ready + .clk_clk (), // clk.clk + .reset_reset_n () // reset.reset_n + ); +