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大概没啥问题

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This commit is contained in:
iridiumR 2022-04-12 16:38:43 +08:00
parent 25530c5d7c
commit 9aa7446b7c
5 changed files with 122 additions and 119 deletions
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171
Quartus/v3/Waveform.vwf
View file

@ -7,7 +7,7 @@
vlib work
vlog -work work jyh_4490_3.vo
vlog -work work Waveform.vwf.vt
vsim -voptargs=+acc -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_entry_vlg_vec_tst
vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_3_entry_vlg_vec_tst
vcd file -direction jyh_4490_3.msim.vcd
vcd add -internal jyh_4490_3_entry_vlg_vec_tst/*
vcd add -internal jyh_4490_3_entry_vlg_vec_tst/i1/*
@ -20,7 +20,6 @@ proc simTimestamp {} {
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
@ -39,7 +38,6 @@ proc simTimestamp {} {
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
@ -338,16 +336,6 @@ SIGNAL("CO")
PARENT = "";
}
SIGNAL("clk2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("code")
{
VALUE_TYPE = NINE_LEVEL_BIT;
@ -662,20 +650,6 @@ TRANSITION_LIST("CO")
}
}
TRANSITION_LIST("clk2")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 200;
LEVEL 0 FOR 2.5;
LEVEL 1 FOR 2.5;
}
}
}
TRANSITION_LIST("code[6]")
{
NODE
@ -768,7 +742,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "clk2";
CHANNEL = "clr";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
@ -777,7 +751,7 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "clr";
CHANNEL = "upd";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
@ -786,30 +760,21 @@ DISPLAY_LINE
DISPLAY_LINE
{
CHANNEL = "upd";
CHANNEL = "en";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "en";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "in0";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 5;
TREE_INDEX = 4;
TREE_LEVEL = 0;
CHILDREN = 6, 7, 8, 9;
CHILDREN = 5, 6, 7, 8;
}
DISPLAY_LINE
@ -817,9 +782,9 @@ DISPLAY_LINE
CHANNEL = "in0[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 6;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 5;
PARENT = 4;
}
DISPLAY_LINE
@ -827,9 +792,9 @@ DISPLAY_LINE
CHANNEL = "in0[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 7;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 5;
PARENT = 4;
}
DISPLAY_LINE
@ -837,9 +802,9 @@ DISPLAY_LINE
CHANNEL = "in0[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 8;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 5;
PARENT = 4;
}
DISPLAY_LINE
@ -847,9 +812,9 @@ DISPLAY_LINE
CHANNEL = "in0[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 9;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 5;
PARENT = 4;
}
DISPLAY_LINE
@ -857,9 +822,9 @@ DISPLAY_LINE
CHANNEL = "in1";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 10;
TREE_INDEX = 9;
TREE_LEVEL = 0;
CHILDREN = 11, 12, 13, 14;
CHILDREN = 10, 11, 12, 13;
}
DISPLAY_LINE
@ -867,9 +832,9 @@ DISPLAY_LINE
CHANNEL = "in1[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 11;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 10;
PARENT = 9;
}
DISPLAY_LINE
@ -877,9 +842,9 @@ DISPLAY_LINE
CHANNEL = "in1[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 12;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 10;
PARENT = 9;
}
DISPLAY_LINE
@ -887,9 +852,9 @@ DISPLAY_LINE
CHANNEL = "in1[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 13;
TREE_INDEX = 12;
TREE_LEVEL = 1;
PARENT = 10;
PARENT = 9;
}
DISPLAY_LINE
@ -897,9 +862,9 @@ DISPLAY_LINE
CHANNEL = "in1[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 14;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 10;
PARENT = 9;
}
DISPLAY_LINE
@ -907,7 +872,7 @@ DISPLAY_LINE
CHANNEL = "load";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 15;
TREE_INDEX = 14;
TREE_LEVEL = 0;
}
@ -916,7 +881,7 @@ DISPLAY_LINE
CHANNEL = "CO";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 16;
TREE_INDEX = 15;
TREE_LEVEL = 0;
}
@ -925,9 +890,9 @@ DISPLAY_LINE
CHANNEL = "out0";
EXPAND_STATUS = EXPANDED;
RADIX = Unsigned;
TREE_INDEX = 17;
TREE_INDEX = 16;
TREE_LEVEL = 0;
CHILDREN = 18, 19, 20, 21;
CHILDREN = 17, 18, 19, 20;
}
DISPLAY_LINE
@ -935,9 +900,9 @@ DISPLAY_LINE
CHANNEL = "out0[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 18;
TREE_INDEX = 17;
TREE_LEVEL = 1;
PARENT = 17;
PARENT = 16;
}
DISPLAY_LINE
@ -945,9 +910,9 @@ DISPLAY_LINE
CHANNEL = "out0[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 19;
TREE_INDEX = 18;
TREE_LEVEL = 1;
PARENT = 17;
PARENT = 16;
}
DISPLAY_LINE
@ -955,9 +920,9 @@ DISPLAY_LINE
CHANNEL = "out0[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 20;
TREE_INDEX = 19;
TREE_LEVEL = 1;
PARENT = 17;
PARENT = 16;
}
DISPLAY_LINE
@ -965,9 +930,9 @@ DISPLAY_LINE
CHANNEL = "out0[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 21;
TREE_INDEX = 20;
TREE_LEVEL = 1;
PARENT = 17;
PARENT = 16;
}
DISPLAY_LINE
@ -975,9 +940,9 @@ DISPLAY_LINE
CHANNEL = "out1";
EXPAND_STATUS = EXPANDED;
RADIX = Unsigned;
TREE_INDEX = 22;
TREE_INDEX = 21;
TREE_LEVEL = 0;
CHILDREN = 23, 24, 25, 26;
CHILDREN = 22, 23, 24, 25;
}
DISPLAY_LINE
@ -985,9 +950,9 @@ DISPLAY_LINE
CHANNEL = "out1[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 23;
TREE_INDEX = 22;
TREE_LEVEL = 1;
PARENT = 22;
PARENT = 21;
}
DISPLAY_LINE
@ -995,9 +960,9 @@ DISPLAY_LINE
CHANNEL = "out1[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 24;
TREE_INDEX = 23;
TREE_LEVEL = 1;
PARENT = 22;
PARENT = 21;
}
DISPLAY_LINE
@ -1005,9 +970,9 @@ DISPLAY_LINE
CHANNEL = "out1[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 25;
TREE_INDEX = 24;
TREE_LEVEL = 1;
PARENT = 22;
PARENT = 21;
}
DISPLAY_LINE
@ -1015,9 +980,9 @@ DISPLAY_LINE
CHANNEL = "out1[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 26;
TREE_INDEX = 25;
TREE_LEVEL = 1;
PARENT = 22;
PARENT = 21;
}
DISPLAY_LINE
@ -1025,9 +990,9 @@ DISPLAY_LINE
CHANNEL = "code";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 27;
TREE_INDEX = 26;
TREE_LEVEL = 0;
CHILDREN = 28, 29, 30, 31, 32, 33, 34;
CHILDREN = 27, 28, 29, 30, 31, 32, 33;
}
DISPLAY_LINE
@ -1035,9 +1000,9 @@ DISPLAY_LINE
CHANNEL = "code[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 28;
TREE_INDEX = 27;
TREE_LEVEL = 1;
PARENT = 27;
PARENT = 26;
}
DISPLAY_LINE
@ -1045,9 +1010,9 @@ DISPLAY_LINE
CHANNEL = "code[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 29;
TREE_INDEX = 28;
TREE_LEVEL = 1;
PARENT = 27;
PARENT = 26;
}
DISPLAY_LINE
@ -1055,9 +1020,9 @@ DISPLAY_LINE
CHANNEL = "code[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 30;
TREE_INDEX = 29;
TREE_LEVEL = 1;
PARENT = 27;
PARENT = 26;
}
DISPLAY_LINE
@ -1065,9 +1030,9 @@ DISPLAY_LINE
CHANNEL = "code[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 31;
TREE_INDEX = 30;
TREE_LEVEL = 1;
PARENT = 27;
PARENT = 26;
}
DISPLAY_LINE
@ -1075,9 +1040,9 @@ DISPLAY_LINE
CHANNEL = "code[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 32;
TREE_INDEX = 31;
TREE_LEVEL = 1;
PARENT = 27;
PARENT = 26;
}
DISPLAY_LINE
@ -1085,9 +1050,9 @@ DISPLAY_LINE
CHANNEL = "code[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 33;
TREE_INDEX = 32;
TREE_LEVEL = 1;
PARENT = 27;
PARENT = 26;
}
DISPLAY_LINE
@ -1095,9 +1060,9 @@ DISPLAY_LINE
CHANNEL = "code[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 34;
TREE_INDEX = 33;
TREE_LEVEL = 1;
PARENT = 27;
PARENT = 26;
}
DISPLAY_LINE
@ -1105,9 +1070,9 @@ DISPLAY_LINE
CHANNEL = "sel";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 35;
TREE_INDEX = 34;
TREE_LEVEL = 0;
CHILDREN = 36, 37;
CHILDREN = 35, 36;
}
DISPLAY_LINE
@ -1115,9 +1080,9 @@ DISPLAY_LINE
CHANNEL = "sel[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 36;
TREE_INDEX = 35;
TREE_LEVEL = 1;
PARENT = 35;
PARENT = 34;
}
DISPLAY_LINE
@ -1125,9 +1090,9 @@ DISPLAY_LINE
CHANNEL = "sel[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 37;
TREE_INDEX = 36;
TREE_LEVEL = 1;
PARENT = 35;
PARENT = 34;
}
TIME_BAR

5
Quartus/v3/jyh_4490_3.qsf
View file

@ -97,7 +97,6 @@ set_location_assignment PIN_121 -to sel[5]
set_location_assignment PIN_113 -to sel[6]
set_location_assignment PIN_120 -to sel[7]
set_global_assignment -name VERILOG_FILE jyh_4490_3_divide.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Precision Synthesis"
set_global_assignment -name EDA_LMF_FILE mentor.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
@ -107,4 +106,6 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name VERILOG_FILE jyh_4490_3_simpleEncoder.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

7
Quartus/v3/jyh_4490_3_divide.v
View file

@ -2,11 +2,14 @@ module jyh_4490_3_divide(clkin,clkout);
input clkin;
output reg clkout=0;
reg [4:0] temp;
reg [2:0] temp;
always@(posedge clkin)
begin
temp<=temp+1;
if(temp==0)
clkout=~clkout;
end
endmodule
endmodule

31
Quartus/v3/jyh_4490_3_entry.v
View file

@ -1,7 +1,7 @@
module jyh_4490_3_entry(out1, out0, code, sel, CO,
// 十位输出 个位输出 数码管型码 数码管位码 进/借位标志位
in1, in0, load, clk, clk2, clr, en, upd);
// 十位装载 个位装载 装载信号 计数时钟信号 数码管时钟 清零信号 使能信号 正反计数标志位
in1, in0, load, clk, clr, en, upd);
// 十位装载 个位装载 装载信号 计数时钟信号 清零信号 使能信号 正反计数标志位
output [3:0] out1;
output [3:0] out0;
@ -10,14 +10,14 @@ output [7:0] sel;
output CO;
input [3:0] in1;
input [3:0] in0;
input clk,load,clr,en,upd,clk2;
input clk,load,clr,en,upd;
wire subclk;
jyh_4490_3_divide(
.clkin(clk),
.clkout(subclk)
);
//wire subclk;
//jyh_4490_3_divide(
//.clkin(clk),
//.clkout(subclk)
//);
//个位计数器
@ -44,12 +44,19 @@ jyh_4490_3_counter c1(
//四位数码管译码器
jyh_4490_3_encoder e1(
//jyh_4490_3_encoder e1(
//.codeout(code),
//.d1(out0),
//.d2(out1),
//.clk(clk),
//.sel(sel[1:0])
//);
jyh_4490_3_simpleEncoder(
.codeout(code),
.d1(out0),
.d2(out1),
.clk(clk2),
.sel(sel[1:0])
.clk(clk),
.sel(sel[0:0])
);
endmodule

27
Quartus/v3/jyh_4490_3_simpleEncoder.v Normal file
View file

@ -0,0 +1,27 @@
//七段一位译码器
module jyh_4490_3_simpleEncoder(sel,codeout,clk, d1);
input clk;
input [6:0] d1;
output reg sel; //位选
output reg [6:0] codeout; //型码
always @(clk)
begin
case (d1)
4'd0: codeout<=7'b1111110;
4'd1: codeout<=7'b0110000;
4'd2: codeout<=7'b1101101;
4'd3: codeout<=7'b1111001;
4'd4: codeout<=7'b0110011;
4'd5: codeout<=7'b1011011;
4'd6: codeout<=7'b1011111;
4'd7: codeout<=7'b1110000;
4'd8: codeout<=7'b1111111;
4'd9: codeout<=7'b1111011;
default: codeout<=7'bx;
endcase
end
endmodule