有了，但需要更多魔法
This commit is contained in:
iridiumR
parent
ef40a7c042
commit
9af59fd792
11 changed files with 821 additions and 1 deletions
31
Quartus/v6/jyh_4490_6.qpf
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31
Quartus/v6/jyh_4490_6.qpf
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@ -0,0 +1,31 @@
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# -------------------------------------------------------------------------- #
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||||
#
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||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
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||||
#
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||||
# Quartus Prime
|
||||
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
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# Date created = 21:39:46 五月 09, 2022
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||||
#
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||||
# -------------------------------------------------------------------------- #
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||||
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QUARTUS_VERSION = "21.1"
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DATE = "21:39:46 五月 09, 2022"
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# Revisions
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||||
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PROJECT_REVISION = "jyh_4490_6"
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56
Quartus/v6/jyh_4490_6.qsf
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56
Quartus/v6/jyh_4490_6.qsf
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|
@ -0,0 +1,56 @@
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|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
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||||
# Quartus Prime
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||||
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
# Date created = 21:39:46 五月 09, 2022
|
||||
#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# jyh_4490_6_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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||||
#
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||||
# 2) Intel recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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||||
# and any changes you make may be lost or overwritten.
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||||
#
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||||
# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE6E22C8
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set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_mstate
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:39:46 五月 09, 2022"
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set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name VERILOG_FILE jyh_4490_mstate.v
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set_global_assignment -name VERILOG_FILE jyh_4490_6_testbench.v
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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||||
44
Quartus/v6/jyh_4490_6_testbench.v
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44
Quartus/v6/jyh_4490_6_testbench.v
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`timescale 1ns/1ns
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module jyh_4490_6_testbench;
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reg clk;
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reg in;
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reg en;
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wire out;
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wire [19:0] cnt;
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initial begin
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clk=0;
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in=0;
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en=1;
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end
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always#10 clk=~clk;
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always#20000000
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begin
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in=0;
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repeat(5)
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begin
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in=1;
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#1000000;
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in=0;
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#1000000;
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end
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in=1;
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#35000000
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repeat(5)
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begin
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in=0;
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#1000000;
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in=1;
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#1000000;
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end
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in=0;
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end
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jyh_4490_mstate M1(
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.clk(clk),
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.in(in),
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.out(out),
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.cnt(cnt));
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endmodule
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53
Quartus/v6/jyh_4490_mstate.v
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53
Quartus/v6/jyh_4490_mstate.v
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module jyh_4490_mstate(clk,in,en,out,cnt);
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input clk,in,en;
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output reg out;
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output reg [19:0] cnt=0;
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reg[1:0] state=0;
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parameter s0=0,s1=1,s2=2,s3=3;
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parameter TARGET=750000; //50mhz 15ms
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always @(posedge clk)
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if(!en)
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state=s0;
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else
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case(state)
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s0:
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begin
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if(in)
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state=s1;
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out=0;
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end
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s1:
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if(cnt<TARGET)
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cnt=cnt+1;
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else
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begin
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if(in)
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state=s2;
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else
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state=s0;
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cnt=0;
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end
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s2:
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begin
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if(in)
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state=s2;
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else
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state=s3;
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out=1;
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end
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s3:
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if(cnt<TARGET)
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cnt=cnt+1;
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else
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begin
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if(in)
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state=s2;
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else
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state=s0;
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cnt=0;
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end
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endcase
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endmodule
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15
Quartus/v6_testbench/jyh_4490_6.cr.mti
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15
Quartus/v6_testbench/jyh_4490_6.cr.mti
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@ -0,0 +1,15 @@
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/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module jyh_4490_6_testbench
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Top level modules:
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jyh_4490_6_testbench
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} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
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Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
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-- Compiling module jyh_4490_mstate
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Top level modules:
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jyh_4490_mstate
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} {} {}}
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469
Quartus/v6_testbench/jyh_4490_6.mpf
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469
Quartus/v6_testbench/jyh_4490_6.mpf
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@ -0,0 +1,469 @@
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; Copyright 1991-2009 Mentor Graphics Corporation
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;
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; All Rights Reserved.
|
||||
;
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||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
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; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
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||||
;
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[Library]
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std = $MODEL_TECH/../std
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ieee = $MODEL_TECH/../ieee
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verilog = $MODEL_TECH/../verilog
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vital2000 = $MODEL_TECH/../vital2000
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std_developerskit = $MODEL_TECH/../std_developerskit
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synopsys = $MODEL_TECH/../synopsys
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modelsim_lib = $MODEL_TECH/../modelsim_lib
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sv_std = $MODEL_TECH/../sv_std
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; Altera Primitive libraries
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;
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; VHDL Section
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;
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altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
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altera = $MODEL_TECH/../altera/vhdl/altera
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altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
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lpm = $MODEL_TECH/../altera/vhdl/220model
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220model = $MODEL_TECH/../altera/vhdl/220model
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maxii = $MODEL_TECH/../altera/vhdl/maxii
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maxv = $MODEL_TECH/../altera/vhdl/maxv
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||||
fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
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||||
sgate = $MODEL_TECH/../altera/vhdl/sgate
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||||
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
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||||
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
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||||
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
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||||
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
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||||
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
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||||
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
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||||
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
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||||
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
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||||
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
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||||
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
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||||
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
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||||
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
||||
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
||||
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
||||
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
||||
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
||||
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
||||
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
||||
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
||||
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
||||
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
||||
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
|
||||
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
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||||
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
|
||||
cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
||||
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
||||
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
||||
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
||||
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
||||
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
||||
fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
|
||||
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
||||
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
||||
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
||||
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
||||
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
||||
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
||||
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
||||
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
||||
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
||||
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
||||
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
||||
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
||||
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
||||
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
||||
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
||||
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
||||
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
||||
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
||||
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
||||
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
||||
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
||||
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
||||
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
||||
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
||||
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
||||
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
||||
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
|
||||
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
|
||||
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
|
||||
cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
|
||||
|
||||
work = work
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = ps
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 100 ns
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
suppress = 3116
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
[Project]
|
||||
** Warning: ; Warning -- Do not edit the project properties directly.
|
||||
; Property names are dynamic in nature and property
|
||||
; values have special syntax. Changing property data directly
|
||||
; can result in a corrupt MPF file. All project properties
|
||||
; can be modified through project window dialogs.
|
||||
Project_Version = 6
|
||||
Project_DefaultLib = work
|
||||
Project_SortMethod = unused
|
||||
Project_Files_Count = 2
|
||||
Project_File_0 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v
|
||||
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652112121 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||
Project_File_1 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
|
||||
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1652112079 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||
Project_Sim_Count = 1
|
||||
Project_Sim_0 = Simulation 1
|
||||
Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_6_testbench folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {}
|
||||
Project_Folder_Count = 0
|
||||
Echo_Compile_Output = 0
|
||||
Save_Compile_Report = 1
|
||||
Project_Opt_Count = 0
|
||||
ForceSoftPaths = 0
|
||||
ProjectStatusDelay = 5000
|
||||
VERILOG_DoubleClick = Edit
|
||||
VERILOG_CustomDoubleClick =
|
||||
SYSTEMVERILOG_DoubleClick = Edit
|
||||
SYSTEMVERILOG_CustomDoubleClick =
|
||||
VHDL_DoubleClick = Edit
|
||||
VHDL_CustomDoubleClick =
|
||||
PSL_DoubleClick = Edit
|
||||
PSL_CustomDoubleClick =
|
||||
TEXT_DoubleClick = Edit
|
||||
TEXT_CustomDoubleClick =
|
||||
SYSTEMC_DoubleClick = Edit
|
||||
SYSTEMC_CustomDoubleClick =
|
||||
TCL_DoubleClick = Edit
|
||||
TCL_CustomDoubleClick =
|
||||
MACRO_DoubleClick = Edit
|
||||
MACRO_CustomDoubleClick =
|
||||
VCD_DoubleClick = Edit
|
||||
VCD_CustomDoubleClick =
|
||||
SDF_DoubleClick = Edit
|
||||
SDF_CustomDoubleClick =
|
||||
XML_DoubleClick = Edit
|
||||
XML_CustomDoubleClick =
|
||||
LOGFILE_DoubleClick = Edit
|
||||
LOGFILE_CustomDoubleClick =
|
||||
UCDB_DoubleClick = Edit
|
||||
UCDB_CustomDoubleClick =
|
||||
TDB_DoubleClick = Edit
|
||||
TDB_CustomDoubleClick =
|
||||
UPF_DoubleClick = Edit
|
||||
UPF_CustomDoubleClick =
|
||||
PCF_DoubleClick = Edit
|
||||
PCF_CustomDoubleClick =
|
||||
PROJECT_DoubleClick = Edit
|
||||
PROJECT_CustomDoubleClick =
|
||||
VRM_DoubleClick = Edit
|
||||
VRM_CustomDoubleClick =
|
||||
DEBUGDATABASE_DoubleClick = Edit
|
||||
DEBUGDATABASE_CustomDoubleClick =
|
||||
DEBUGARCHIVE_DoubleClick = Edit
|
||||
DEBUGARCHIVE_CustomDoubleClick =
|
||||
Project_Major_Version = 2020
|
||||
Project_Minor_Version = 1
|
||||
92
Quartus/v6_testbench/transcript
Normal file
92
Quartus/v6_testbench/transcript
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
# Compile of jyh_4490_6_testbench.v was successful.
|
||||
# Compile of jyh_4490_mstate.v was successful.
|
||||
# 2 compiles, 0 failed with no errors.
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# vsim work.jyh_4490_6_testbench
|
||||
# Start time: 23:55:10 on May 09,2022
|
||||
# Loading work.jyh_4490_6_testbench
|
||||
# Loading work.jyh_4490_mstate
|
||||
# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'.
|
||||
# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39
|
||||
# Error loading design
|
||||
# End time: 23:55:10 on May 09,2022, Elapsed time: 0:00:00
|
||||
# Errors: 1, Warnings: 7
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# vsim work.jyh_4490_6_testbench
|
||||
# Start time: 23:55:11 on May 09,2022
|
||||
# Loading work.jyh_4490_6_testbench
|
||||
# Loading work.jyh_4490_mstate
|
||||
# ** Error (suppressible): (vsim-3053) Illegal output or inout port connection for port 'cnt'.
|
||||
# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 39
|
||||
# Error loading design
|
||||
# End time: 23:55:11 on May 09,2022, Elapsed time: 0:00:00
|
||||
# Errors: 1, Warnings: 1
|
||||
# can't read "Startup(-L)": no such element in array
|
||||
# Load canceled
|
||||
# Compile of jyh_4490_6_testbench.v failed with 1 errors.
|
||||
# Compile of jyh_4490_6_testbench.v was successful.
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# vsim work.jyh_4490_6_testbench
|
||||
# Start time: 23:57:01 on May 09,2022
|
||||
# Loading work.jyh_4490_6_testbench
|
||||
# Loading work.jyh_4490_mstate
|
||||
add wave -position end sim:/jyh_4490_6_testbench/clk
|
||||
add wave -position end sim:/jyh_4490_6_testbench/clr
|
||||
add wave -position end sim:/jyh_4490_6_testbench/in
|
||||
add wave -position end sim:/jyh_4490_6_testbench/out
|
||||
add wave -position end sim:/jyh_4490_6_testbench/cnt
|
||||
run -all
|
||||
# Compile of jyh_4490_6_testbench.v was successful.
|
||||
# Compile of jyh_4490_mstate.v was successful.
|
||||
# 2 compiles, 0 failed with no errors.
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# End time: 23:59:24 on May 09,2022, Elapsed time: 0:02:23
|
||||
# Errors: 0, Warnings: 4
|
||||
# vsim work.jyh_4490_6_testbench
|
||||
# Start time: 23:59:24 on May 09,2022
|
||||
# Loading work.jyh_4490_6_testbench
|
||||
# Loading work.jyh_4490_mstate
|
||||
add wave -position end sim:/jyh_4490_6_testbench/clk
|
||||
add wave -position end sim:/jyh_4490_6_testbench/in
|
||||
add wave -position end sim:/jyh_4490_6_testbench/out
|
||||
add wave -position end sim:/jyh_4490_6_testbench/cnt
|
||||
run -all
|
||||
# Compile of jyh_4490_6_testbench.v was successful.
|
||||
# Compile of jyh_4490_mstate.v was successful.
|
||||
# 2 compiles, 0 failed with no errors.
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# running
|
||||
vsim work.jyh_4490_6_testbench
|
||||
# End time: 00:03:02 on May 10,2022, Elapsed time: 0:03:38
|
||||
# Errors: 0, Warnings: 2
|
||||
# vsim work.jyh_4490_6_testbench
|
||||
# Start time: 00:03:02 on May 10,2022
|
||||
# Loading work.jyh_4490_6_testbench
|
||||
# Loading work.jyh_4490_mstate
|
||||
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'M1'. Expected 5, found 4.
|
||||
# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench/M1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v Line: 38
|
||||
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v(38): [TFMPC] - Missing connection for port 'en'.
|
||||
add wave -position end sim:/jyh_4490_6_testbench/clk
|
||||
add wave -position end sim:/jyh_4490_6_testbench/in
|
||||
add wave -position end sim:/jyh_4490_6_testbench/en
|
||||
add wave -position end sim:/jyh_4490_6_testbench/out
|
||||
add wave -position end sim:/jyh_4490_6_testbench/cnt
|
||||
run -all
|
||||
# Break key hit
|
||||
# Simulation stop requested.
|
||||
# End time: 00:05:02 on May 10,2022, Elapsed time: 0:02:00
|
||||
# Errors: 0, Warnings: 4
|
||||
57
Quartus/v6_testbench/work/_info
Normal file
57
Quartus/v6_testbench/work/_info
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
m255
|
||||
K4
|
||||
z2
|
||||
!s11f vlog 2020.1 2020.02, Feb 28 2020
|
||||
13
|
||||
!s112 1.1
|
||||
!i10d 8192
|
||||
!i10e 25
|
||||
!i10f 100
|
||||
cModel Technology
|
||||
Z0 d/home/ir/Documents/codelib/Quartus/v6_testbench
|
||||
vjyh_4490_6_testbench
|
||||
Z1 !s110 1652112137
|
||||
!i10b 1
|
||||
!s100 9RmKL5c:1Ye3BFU:0J9]`0
|
||||
Z2 !s11b Dg1SIo80bB@j0V0VzS_@n1
|
||||
Id==[MRQOC85_S3Uml<2>03
|
||||
Z3 VDg1SIo80bB@j0V0VzS_@n1
|
||||
R0
|
||||
w1652112121
|
||||
8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v
|
||||
F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v
|
||||
!i122 5
|
||||
L0 2 43
|
||||
Z4 OV;L;2020.1;71
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z5 !s108 1652112137.000000
|
||||
!s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v|
|
||||
!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v|
|
||||
!i113 1
|
||||
Z6 o-work work
|
||||
Z7 tCvgOpt 0
|
||||
vjyh_4490_mstate
|
||||
R1
|
||||
!i10b 1
|
||||
!s100 k6`3d<mJf9V5FF52Yi=aD2
|
||||
R2
|
||||
I[WM>_8l:B?R5kVbE<[il30
|
||||
R3
|
||||
R0
|
||||
w1652112079
|
||||
8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
|
||||
F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v
|
||||
!i122 6
|
||||
L0 1 53
|
||||
R4
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R5
|
||||
!s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v|
|
||||
!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v|
|
||||
!i113 1
|
||||
R6
|
||||
R7
|
||||
BIN
Quartus/v6_testbench/work/_lib1_0.qpg
Normal file
BIN
Quartus/v6_testbench/work/_lib1_0.qpg
Normal file
Binary file not shown.
4
Quartus/v6_testbench/work/_vmake
Normal file
4
Quartus/v6_testbench/work/_vmake
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
m255
|
||||
K4
|
||||
z0
|
||||
cModel Technology
|
||||
|
|
@ -1,4 +1,3 @@
|
|||
#include "dialog.h"
|
||||
#include "widget.h"
|
||||
#include <QApplication>
|
||||
|
||||
|
|
|
|||
Reference in a new issue