quartus 实验
This commit is contained in:
iridiumR
parent
feb6e05c47
commit
a0651561f3
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@ -111,3 +111,45 @@ Thumbs.db
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# --------
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*.dll
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*.exe
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# ignore Quartus II generated files
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*_generation_script*
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*_inst.vhd
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*.bak
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*.cmp
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*.done
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*.eqn
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*.hex
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*.html
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*.jdi
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*.jpg
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# *.mif
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*.pin
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*.pof
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*.ptf.*
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*.qar
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*.qarlog
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*.qws
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*.rpt
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*.smsg
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*.sof
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*.sopc_builder
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*.summary
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*.tcl
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*.txt # Explicitly add any text files used
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*~
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*example*
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*sopc_*
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# *.sdc # I want those timing files
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# ignore Quartus II generated folders
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*/incremental_db/
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**/simulation/**
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*/timing/
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**/incremental_db/**
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db/
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**/output_files/**
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PLLJ_PLLSPE_INFO.txt
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@ -0,0 +1,31 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2021 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
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# Date created = 22:59:53 三月 29, 2022
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#
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# -------------------------------------------------------------------------- #
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QUARTUS_VERSION = "21.1"
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DATE = "22:59:53 三月 29, 2022"
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# Revisions
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PROJECT_REVISION = "jyh_4490_1"
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@ -0,0 +1,51 @@
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# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2021 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
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# Date created = 22:59:53 三月 29, 2022
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# jyh_4490_1_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Intel recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE6E22C8
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set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_1
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:59:53 三月 29, 2022"
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set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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@ -0,0 +1,504 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_2 -c jyh_4490_2 --vector_source="/home/ir/Documents/codelib/Quartus/v2/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_2 -c jyh_4490_2 --vector_source="/home/ir/Documents/codelib/Quartus/v2/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/" jyh_4490_2 -c jyh_4490_2</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/" jyh_4490_2 -c jyh_4490_2</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_2.vo
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vlog -work work Waveform.vwf.vt
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vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.v2_entry_4490_vlg_vec_tst
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vcd file -direction jyh_4490_2.msim.vcd
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vcd add -internal v2_entry_4490_vlg_vec_tst/*
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vcd add -internal v2_entry_4490_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_2.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.v2_entry_4490_vlg_vec_tst
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vcd file -direction jyh_4490_2.msim.vcd
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vcd add -internal v2_entry_4490_vlg_vec_tst/*
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vcd add -internal v2_entry_4490_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2021 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Intel Program License
|
||||
Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
the Intel FPGA IP License Agreement, or other applicable license
|
||||
agreement, including, without limitation, that your use is for
|
||||
the sole purpose of programming logic devices manufactured by
|
||||
Intel and sold by Intel or its authorized distributors. Please
|
||||
refer to the applicable agreement for further details, at
|
||||
https://fpgasoftware.intel.com/eula.
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||||
*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("Qout")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 3;
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LSB_INDEX = 0;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("Qout[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "Qout";
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}
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SIGNAL("Qout[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "Qout";
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}
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SIGNAL("Qout[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "Qout";
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}
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SIGNAL("clk_in")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("code_out")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = BUS;
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WIDTH = 7;
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LSB_INDEX = 0;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("code_out[6]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "code_out";
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}
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SIGNAL("code_out[5]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "code_out";
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}
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SIGNAL("code_out[4]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "code_out";
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}
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SIGNAL("code_out[3]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "code_out";
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}
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SIGNAL("code_out[2]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "code_out";
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}
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SIGNAL("code_out[1]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "code_out";
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}
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SIGNAL("code_out[0]")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "code_out";
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}
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SIGNAL("enable_in")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("seg_out")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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TRANSITION_LIST("Qout[2]")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
|
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}
|
||||
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TRANSITION_LIST("Qout[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
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REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("Qout[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
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||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("clk_in")
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||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
NODE
|
||||
{
|
||||
REPEAT = 50;
|
||||
LEVEL 0 FOR 10.0;
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||||
LEVEL 1 FOR 10.0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("code_out[6]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("code_out[5]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
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||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("code_out[4]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("code_out[3]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("code_out[2]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("code_out[1]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("code_out[0]")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("enable_in")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL 0 FOR 120.0;
|
||||
LEVEL 1 FOR 880.0;
|
||||
}
|
||||
}
|
||||
|
||||
TRANSITION_LIST("seg_out")
|
||||
{
|
||||
NODE
|
||||
{
|
||||
REPEAT = 1;
|
||||
LEVEL X FOR 1000.0;
|
||||
}
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "clk_in";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 0;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "enable_in";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 1;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "Qout";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 2;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 3, 4, 5;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "Qout[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 3;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 2;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "Qout[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 4;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 2;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "Qout[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 5;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 2;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out";
|
||||
EXPAND_STATUS = EXPANDED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 6;
|
||||
TREE_LEVEL = 0;
|
||||
CHILDREN = 7, 8, 9, 10, 11, 12, 13;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out[6]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 7;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out[5]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 8;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out[4]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 9;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out[3]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 10;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out[2]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 11;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out[1]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 12;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "code_out[0]";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 13;
|
||||
TREE_LEVEL = 1;
|
||||
PARENT = 6;
|
||||
}
|
||||
|
||||
DISPLAY_LINE
|
||||
{
|
||||
CHANNEL = "seg_out";
|
||||
EXPAND_STATUS = COLLAPSED;
|
||||
RADIX = Binary;
|
||||
TREE_INDEX = 14;
|
||||
TREE_LEVEL = 0;
|
||||
}
|
||||
|
||||
TIME_BAR
|
||||
{
|
||||
TIME = 0;
|
||||
MASTER = TRUE;
|
||||
}
|
||||
;
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
# Date created = 21:26:12 三月 29, 2022
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "21.1"
|
||||
DATE = "21:26:12 三月 29, 2022"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "jyh_4490_2"
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 2021 Intel Corporation. All rights reserved.
|
||||
# Your use of Intel Corporation's design tools, logic functions
|
||||
# and other software and tools, and any partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Intel Program License
|
||||
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||||
# the Intel FPGA IP License Agreement, or other applicable license
|
||||
# agreement, including, without limitation, that your use is for
|
||||
# the sole purpose of programming logic devices manufactured by
|
||||
# Intel and sold by Intel or its authorized distributors. Please
|
||||
# refer to the applicable agreement for further details, at
|
||||
# https://fpgasoftware.intel.com/eula.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus Prime
|
||||
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
|
||||
# Date created = 21:26:12 三月 29, 2022
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# jyh_4490_2_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Intel recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus Prime software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "Cyclone IV E"
|
||||
set_global_assignment -name DEVICE EP4CE6E22C8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY v2_entry_4490
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:26:12 三月 29, 2022"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
|
||||
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
||||
set_global_assignment -name VERILOG_FILE v2_entry_4490.v
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_2_2.v
|
||||
set_global_assignment -name VERILOG_FILE jyh_4490_2_1.v
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
|
||||
set_location_assignment PIN_31 -to enable_in
|
||||
set_location_assignment PIN_46 -to Qout[0]
|
||||
set_location_assignment PIN_50 -to Qout[1]
|
||||
set_location_assignment PIN_52 -to Qout[2]
|
||||
set_location_assignment PIN_88 -to clk_in
|
||||
set_location_assignment PIN_43 -to code_out[6]
|
||||
set_location_assignment PIN_44 -to code_out[5]
|
||||
set_location_assignment PIN_39 -to code_out[4]
|
||||
set_location_assignment PIN_42 -to code_out[3]
|
||||
set_location_assignment PIN_32 -to code_out[2]
|
||||
set_location_assignment PIN_33 -to code_out[1]
|
||||
set_location_assignment PIN_30 -to code_out[0]
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
//计数器模块
|
||||
module jyh_4490_2_1(clk,en,Q);
|
||||
input clk,en;
|
||||
output reg[2:0] Q;
|
||||
|
||||
always@(posedge clk)
|
||||
begin
|
||||
if(en == 1'b1)
|
||||
begin
|
||||
if(Q<3'd6)
|
||||
Q <= Q + 1'b1;
|
||||
else
|
||||
Q <= 0;
|
||||
end
|
||||
else
|
||||
Q<=0;
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
//译码器模块
|
||||
module jyh_4490_2_2(out,in);
|
||||
input[2:0] in;
|
||||
output[8:0] out;
|
||||
|
||||
reg[7:0] out;
|
||||
|
||||
always @ (in)
|
||||
begin
|
||||
case (in)
|
||||
4'd0: out=7'b0000001;
|
||||
6'd1: out=7'b0000011;
|
||||
4'd2: out=7'b0000111;
|
||||
4'd3: out=7'b0001111;
|
||||
3'd4: out=7'b0011111;
|
||||
3'd5: out=7'b0111111;
|
||||
3'd6: out=7'b0000000;
|
||||
|
||||
default: out=7'bx;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
module v2_entry_4490(clk_in,enable_in,Qout,seg_out,code_out);
|
||||
input clk_in,enable_in;
|
||||
output wire [2:0] Qout;
|
||||
output wire seg_out;
|
||||
output wire [6:0]code_out;
|
||||
|
||||
//调用计数器模块
|
||||
jyh_4490_2_1 counter(
|
||||
.clk(clk_in),
|
||||
.en(enable_in),
|
||||
.Q(Qout));
|
||||
|
||||
//调用译码器模块
|
||||
jyh_4490_2_2 encoder(
|
||||
.in(Qout),
|
||||
.out(code_out));
|
||||
|
||||
endmodule
|
||||
Reference in New Issue