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quartus 实验

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iridiumR 2022-03-29 23:03:53 +08:00
parent feb6e05c47
commit a0651561f3
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42
.gitignore vendored
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@ -111,3 +111,45 @@ Thumbs.db
# -------- # --------
*.dll *.dll
*.exe *.exe
# ignore Quartus II generated files
*_generation_script*
*_inst.vhd
*.bak
*.cmp
*.done
*.eqn
*.hex
*.html
*.jdi
*.jpg
# *.mif
*.pin
*.pof
*.ptf.*
*.qar
*.qarlog
*.qws
*.rpt
*.smsg
*.sof
*.sopc_builder
*.summary
*.tcl
*.txt # Explicitly add any text files used
*~
*example*
*sopc_*
# *.sdc # I want those timing files
# ignore Quartus II generated folders
*/incremental_db/
**/simulation/**
*/timing/
**/incremental_db/**
db/
**/output_files/**
PLLJ_PLLSPE_INFO.txt

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Quartus/v1/jyh_4490_1.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 22:59:53 三月 29, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "21.1"
DATE = "22:59:53 三月 29, 2022"
# Revisions
PROJECT_REVISION = "jyh_4490_1"

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Quartus/v1/jyh_4490_1.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 22:59:53 三月 29, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# jyh_4490_1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY jyh_4490_1
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:59:53 三月 29, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V

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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_2 -c jyh_4490_2 --vector_source="/home/ir/Documents/codelib/Quartus/v2/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_2 -c jyh_4490_2 --vector_source="/home/ir/Documents/codelib/Quartus/v2/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/" jyh_4490_2 -c jyh_4490_2</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v2/simulation/qsim/" jyh_4490_2 -c jyh_4490_2</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work jyh_4490_2.vo
vlog -work work Waveform.vwf.vt
vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.v2_entry_4490_vlg_vec_tst
vcd file -direction jyh_4490_2.msim.vcd
vcd add -internal v2_entry_4490_vlg_vec_tst/*
vcd add -internal v2_entry_4490_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work jyh_4490_2.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.v2_entry_4490_vlg_vec_tst
vcd file -direction jyh_4490_2.msim.vcd
vcd add -internal v2_entry_4490_vlg_vec_tst/*
vcd add -internal v2_entry_4490_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2021 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("Qout")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 3;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("Qout[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "Qout";
}
SIGNAL("Qout[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "Qout";
}
SIGNAL("Qout[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "Qout";
}
SIGNAL("clk_in")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("code_out")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 7;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("code_out[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "code_out";
}
SIGNAL("code_out[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "code_out";
}
SIGNAL("code_out[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "code_out";
}
SIGNAL("code_out[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "code_out";
}
SIGNAL("code_out[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "code_out";
}
SIGNAL("code_out[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "code_out";
}
SIGNAL("code_out[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "code_out";
}
SIGNAL("enable_in")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("seg_out")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("Qout[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Qout[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("Qout[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("clk_in")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
TRANSITION_LIST("code_out[6]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("code_out[5]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("code_out[4]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("code_out[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("code_out[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("code_out[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("code_out[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("enable_in")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 120.0;
LEVEL 1 FOR 880.0;
}
}
TRANSITION_LIST("seg_out")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "clk_in";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "enable_in";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "Qout";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
CHILDREN = 3, 4, 5;
}
DISPLAY_LINE
{
CHANNEL = "Qout[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "Qout[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "Qout[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 2;
}
DISPLAY_LINE
{
CHANNEL = "code_out";
EXPAND_STATUS = EXPANDED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 0;
CHILDREN = 7, 8, 9, 10, 11, 12, 13;
}
DISPLAY_LINE
{
CHANNEL = "code_out[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "code_out[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "code_out[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "code_out[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "code_out[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "code_out[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "code_out[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "seg_out";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 14;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 21:26:12 三月 29, 2022
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "21.1"
DATE = "21:26:12 三月 29, 2022"
# Revisions
PROJECT_REVISION = "jyh_4490_2"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 21:26:12 三月 29, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# jyh_4490_2_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY v2_entry_4490
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:26:12 三月 29, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name VERILOG_FILE v2_entry_4490.v
set_global_assignment -name VERILOG_FILE jyh_4490_2_2.v
set_global_assignment -name VERILOG_FILE jyh_4490_2_1.v
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_location_assignment PIN_31 -to enable_in
set_location_assignment PIN_46 -to Qout[0]
set_location_assignment PIN_50 -to Qout[1]
set_location_assignment PIN_52 -to Qout[2]
set_location_assignment PIN_88 -to clk_in
set_location_assignment PIN_43 -to code_out[6]
set_location_assignment PIN_44 -to code_out[5]
set_location_assignment PIN_39 -to code_out[4]
set_location_assignment PIN_42 -to code_out[3]
set_location_assignment PIN_32 -to code_out[2]
set_location_assignment PIN_33 -to code_out[1]
set_location_assignment PIN_30 -to code_out[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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//计数器模块
module jyh_4490_2_1(clk,en,Q);
input clk,en;
output reg[2:0] Q;
always@(posedge clk)
begin
if(en == 1'b1)
begin
if(Q<3'd6)
Q <= Q + 1'b1;
else
Q <= 0;
end
else
Q<=0;
end
endmodule

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//译码器模块
module jyh_4490_2_2(out,in);
input[2:0] in;
output[8:0] out;
reg[7:0] out;
always @ (in)
begin
case (in)
4'd0: out=7'b0000001;
6'd1: out=7'b0000011;
4'd2: out=7'b0000111;
4'd3: out=7'b0001111;
3'd4: out=7'b0011111;
3'd5: out=7'b0111111;
3'd6: out=7'b0000000;
default: out=7'bx;
endcase
end
endmodule

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module v2_entry_4490(clk_in,enable_in,Qout,seg_out,code_out);
input clk_in,enable_in;
output wire [2:0] Qout;
output wire seg_out;
output wire [6:0]code_out;
//调用计数器模块
jyh_4490_2_1 counter(
.clk(clk_in),
.en(enable_in),
.Q(Qout));
//调用译码器模块
jyh_4490_2_2 encoder(
.in(Qout),
.out(code_out));
endmodule