低级错误
This commit is contained in:
iridiumR
parent
3a5820c98a
commit
af10d60efa
10 changed files with 861 additions and 20 deletions
279
Quartus/v7/Waveform.vwf
Normal file
279
Quartus/v7/Waveform.vwf
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@ -0,0 +1,279 @@
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/*<simulation_settings>
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<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
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<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_7 -c jyh_4490_7 --vector_source="/home/ir/Documents/codelib/Quartus/v7/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
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<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</fnetlist_cmd>
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<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v7/simulation/qsim/" jyh_4490_7 -c jyh_4490_7</tnetlist_cmd>
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<modelsim_script>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_7.vo
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vlog -work work Waveform.vwf.vt
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vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
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vcd file -direction jyh_4490_7.msim.vcd
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script>
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<modelsim_script_timing>onerror {exit -code 1}
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vlib work
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vlog -work work jyh_4490_7.vo
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vlog -work work Waveform.vwf.vt
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vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_7_is_vlg_vec_tst
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vcd file -direction jyh_4490_7.msim.vcd
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/*
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vcd add -internal jyh_4490_7_is_vlg_vec_tst/i1/*
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proc simTimestamp {} {
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echo "Simulation time: $::now ps"
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if { [string equal running [runStatus]] } {
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after 2500 simTimestamp
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}
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}
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after 2500 simTimestamp
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run -all
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quit -f
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</modelsim_script_timing>
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<hdl_lang>verilog</hdl_lang>
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</simulation_settings>*/
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/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 2021 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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*/
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HEADER
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{
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VERSION = 1;
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TIME_UNIT = ns;
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DATA_OFFSET = 0.0;
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DATA_DURATION = 1000.0;
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SIMULATION_TIME = 0.0;
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GRID_PHASE = 0.0;
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GRID_PERIOD = 10.0;
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GRID_DUTY_CYCLE = 50;
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}
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SIGNAL("clk")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("f0")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("f1")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("f2")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = OUTPUT;
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PARENT = "";
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}
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SIGNAL("p")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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SIGNAL("sta")
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{
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VALUE_TYPE = NINE_LEVEL_BIT;
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SIGNAL_TYPE = SINGLE_BIT;
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WIDTH = 1;
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LSB_INDEX = -1;
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DIRECTION = INPUT;
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PARENT = "";
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}
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TRANSITION_LIST("clk")
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{
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NODE
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{
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REPEAT = 1;
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NODE
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{
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REPEAT = 1000;
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LEVEL 0 FOR 0.5;
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LEVEL 1 FOR 0.5;
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}
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}
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}
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TRANSITION_LIST("f0")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 20.0;
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LEVEL 1 FOR 40.0;
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LEVEL 0 FOR 40.0;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 60.0;
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LEVEL 1 FOR 20.0;
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LEVEL 0 FOR 40.0;
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LEVEL 1 FOR 10.0;
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LEVEL 0 FOR 100.0;
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LEVEL 1 FOR 60.0;
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LEVEL 0 FOR 30.0;
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LEVEL 1 FOR 50.0;
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LEVEL 0 FOR 50.0;
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LEVEL 1 FOR 30.0;
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LEVEL 0 FOR 50.0;
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LEVEL 1 FOR 30.0;
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LEVEL 0 FOR 50.0;
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LEVEL 1 FOR 10.0;
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LEVEL 0 FOR 90.0;
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LEVEL 1 FOR 30.0;
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LEVEL 0 FOR 170.0;
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}
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}
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TRANSITION_LIST("f1")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("f2")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL X FOR 1000.0;
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}
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}
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TRANSITION_LIST("p")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 280.0;
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LEVEL 1 FOR 720.0;
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}
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}
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TRANSITION_LIST("sta")
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{
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NODE
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{
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REPEAT = 1;
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LEVEL 0 FOR 660.0;
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LEVEL 1 FOR 340.0;
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}
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}
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DISPLAY_LINE
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{
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CHANNEL = "clk";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 0;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "f0";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 1;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "f1";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 2;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "f2";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 3;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "p";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 4;
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TREE_LEVEL = 0;
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}
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DISPLAY_LINE
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{
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CHANNEL = "sta";
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EXPAND_STATUS = COLLAPSED;
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RADIX = Binary;
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TREE_INDEX = 5;
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TREE_LEVEL = 0;
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}
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TIME_BAR
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{
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TIME = 0;
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MASTER = TRUE;
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}
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;
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@ -55,4 +55,5 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VERILOG_FILE jyh_4490_7_testbench.v
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set_global_assignment -name VERILOG_FILE jyh_4490_7_testbench.v
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -38,28 +38,37 @@ begin
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//shaochong
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//shaochong
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if(p)
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if(p)
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begin
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if(sta)
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if(sta)
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begin
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begin
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if(count>=5*TARGET2)
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if(count2>=5*TARGET2)
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begin
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begin
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f2<=0;
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f2<=0;
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flag2<=0;
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flag2<=0;
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//end of a circle
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//end of a circle
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end
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end
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else if(count==4*TARGET2)
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else if(count2>=4*TARGET2)
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f2<=1;
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f2<=1;
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else if(count2>=3*TARGET2)
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f2<=0;
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else if(count2>=2*TARGET2)
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f2<=1;
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else if(count2>=TARGET2)
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f2<=0;
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end
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end
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if(count>=3*TARGET2)
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else if(count>=3*TARGET2)
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begin
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begin
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f2<=0;
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f2<=0;
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if(!sta)
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flag2<=0;
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flag2<=0;
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//end of a circle
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//end of a circle
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end
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end
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else if(count>=2*TARGET2)
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else if(count>=2*TARGET2)
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f2<=1;
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f2<=1;
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else if(count>=TARGET2)
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else if(count>=TARGET2)
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f2<=0;
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f2<=0;
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|
end
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else
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else
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f2<=f1;
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f2<=f1;
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@ -69,8 +78,9 @@ begin
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count<=count+1;
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count<=count+1;
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else
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else
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count<=0;
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count<=0;
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if(flag2)
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if(flag2)
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count2<=count+1;
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count2<=count2+1;
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else
|
else
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count2<=0;
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count2<=0;
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end
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end
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@ -14,40 +14,40 @@ always #10 clk=~clk;
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always begin
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always begin
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f0=1;
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f0=1;
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#30000;
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#300000;
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f0=0;
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f0=0;
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#70000;
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#700000;
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f0=1;
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f0=1;
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#24000;
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#240000;
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f0=0;
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f0=0;
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#76000;
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#760000;
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f0=1;
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f0=1;
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#18000;
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#180000;
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f0=0;
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f0=0;
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#82000;
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#820000;
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f0=1;
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f0=1;
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#12000;
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#120000;
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f0=0;
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f0=0;
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#80000;
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#800000;
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f0=1;
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f0=1;
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#6000;
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#60000;
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f0=0;
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f0=0;
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#94000;
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#940000;
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|
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end
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end
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always begin
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always begin
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p=0;
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p=0;
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sta=0;
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sta=0;
|
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#600000;
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#6000000;
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p=1;
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p=1;
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#300000;
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#3000000;
|
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sta=1;
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sta=1;
|
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#300000;
|
#3000000;
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||||||
end
|
end
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|
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jyh_4490_7_is C0(
|
jyh_4490_7_is C0(
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|
||||||
8
Quartus/v7_testbench/jyh_4490_7.cr.mti
Normal file
8
Quartus/v7_testbench/jyh_4490_7.cr.mti
Normal file
|
|
@ -0,0 +1,8 @@
|
||||||
|
/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v
|
||||||
|
Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
|
||||||
|
-- Compiling module jyh_4490_7_testbench
|
||||||
|
|
||||||
|
Top level modules:
|
||||||
|
jyh_4490_7_testbench
|
||||||
|
|
||||||
|
} {} {}}
|
||||||
469
Quartus/v7_testbench/jyh_4490_7.mpf
Normal file
469
Quartus/v7_testbench/jyh_4490_7.mpf
Normal file
|
|
@ -0,0 +1,469 @@
|
||||||
|
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||||
|
;
|
||||||
|
; All Rights Reserved.
|
||||||
|
;
|
||||||
|
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||||
|
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||||
|
;
|
||||||
|
|
||||||
|
[Library]
|
||||||
|
std = $MODEL_TECH/../std
|
||||||
|
ieee = $MODEL_TECH/../ieee
|
||||||
|
verilog = $MODEL_TECH/../verilog
|
||||||
|
vital2000 = $MODEL_TECH/../vital2000
|
||||||
|
std_developerskit = $MODEL_TECH/../std_developerskit
|
||||||
|
synopsys = $MODEL_TECH/../synopsys
|
||||||
|
modelsim_lib = $MODEL_TECH/../modelsim_lib
|
||||||
|
sv_std = $MODEL_TECH/../sv_std
|
||||||
|
|
||||||
|
; Altera Primitive libraries
|
||||||
|
;
|
||||||
|
; VHDL Section
|
||||||
|
;
|
||||||
|
altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
|
||||||
|
altera = $MODEL_TECH/../altera/vhdl/altera
|
||||||
|
altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim
|
||||||
|
lpm = $MODEL_TECH/../altera/vhdl/220model
|
||||||
|
220model = $MODEL_TECH/../altera/vhdl/220model
|
||||||
|
maxii = $MODEL_TECH/../altera/vhdl/maxii
|
||||||
|
maxv = $MODEL_TECH/../altera/vhdl/maxv
|
||||||
|
fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm
|
||||||
|
sgate = $MODEL_TECH/../altera/vhdl/sgate
|
||||||
|
arriaii = $MODEL_TECH/../altera/vhdl/arriaii
|
||||||
|
arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi
|
||||||
|
arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip
|
||||||
|
arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz
|
||||||
|
arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi
|
||||||
|
arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip
|
||||||
|
stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv
|
||||||
|
stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi
|
||||||
|
stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip
|
||||||
|
cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv
|
||||||
|
cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi
|
||||||
|
cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip
|
||||||
|
cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive
|
||||||
|
stratixv = $MODEL_TECH/../altera/vhdl/stratixv
|
||||||
|
stratixv_hssi = $MODEL_TECH/../altera/vhdl/stratixv_hssi
|
||||||
|
stratixv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixv_pcie_hip
|
||||||
|
arriavgz = $MODEL_TECH/../altera/vhdl/arriavgz
|
||||||
|
arriavgz_hssi = $MODEL_TECH/../altera/vhdl/arriavgz_hssi
|
||||||
|
arriavgz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriavgz_pcie_hip
|
||||||
|
arriav = $MODEL_TECH/../altera/vhdl/arriav
|
||||||
|
cyclonev = $MODEL_TECH/../altera/vhdl/cyclonev
|
||||||
|
twentynm = $MODEL_TECH/../altera/vhdl/twentynm
|
||||||
|
twentynm_hssi = $MODEL_TECH/../altera/vhdl/twentynm_hssi
|
||||||
|
twentynm_hip = $MODEL_TECH/../altera/vhdl/twentynm_hip
|
||||||
|
cyclone10lp = $MODEL_TECH/../altera/vhdl/cyclone10lp
|
||||||
|
;
|
||||||
|
; Verilog Section
|
||||||
|
;
|
||||||
|
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
|
||||||
|
altera_ver = $MODEL_TECH/../altera/verilog/altera
|
||||||
|
altera_lnsim_ver = $MODEL_TECH/../altera/verilog/altera_lnsim
|
||||||
|
lpm_ver = $MODEL_TECH/../altera/verilog/220model
|
||||||
|
220model_ver = $MODEL_TECH/../altera/verilog/220model
|
||||||
|
maxii_ver = $MODEL_TECH/../altera/verilog/maxii
|
||||||
|
maxv_ver = $MODEL_TECH/../altera/verilog/maxv
|
||||||
|
fiftyfivenm_ver = $MODEL_TECH/../altera/verilog/fiftyfivenm
|
||||||
|
sgate_ver = $MODEL_TECH/../altera/verilog/sgate
|
||||||
|
arriaii_ver = $MODEL_TECH/../altera/verilog/arriaii
|
||||||
|
arriaii_hssi_ver = $MODEL_TECH/../altera/verilog/arriaii_hssi
|
||||||
|
arriaii_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaii_pcie_hip
|
||||||
|
arriaiigz_ver = $MODEL_TECH/../altera/verilog/arriaiigz
|
||||||
|
arriaiigz_hssi_ver = $MODEL_TECH/../altera/verilog/arriaiigz_hssi
|
||||||
|
arriaiigz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriaiigz_pcie_hip
|
||||||
|
stratixiv_ver = $MODEL_TECH/../altera/verilog/stratixiv
|
||||||
|
stratixiv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixiv_hssi
|
||||||
|
stratixiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixiv_pcie_hip
|
||||||
|
stratixv_ver = $MODEL_TECH/../altera/verilog/stratixv
|
||||||
|
stratixv_hssi_ver = $MODEL_TECH/../altera/verilog/stratixv_hssi
|
||||||
|
stratixv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/stratixv_pcie_hip
|
||||||
|
arriavgz_ver = $MODEL_TECH/../altera/verilog/arriavgz
|
||||||
|
arriavgz_hssi_ver = $MODEL_TECH/../altera/verilog/arriavgz_hssi
|
||||||
|
arriavgz_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriavgz_pcie_hip
|
||||||
|
arriav_ver = $MODEL_TECH/../altera/verilog/arriav
|
||||||
|
arriav_hssi_ver = $MODEL_TECH/../altera/verilog/arriav_hssi
|
||||||
|
arriav_pcie_hip_ver = $MODEL_TECH/../altera/verilog/arriav_pcie_hip
|
||||||
|
cyclonev_ver = $MODEL_TECH/../altera/verilog/cyclonev
|
||||||
|
cyclonev_hssi_ver = $MODEL_TECH/../altera/verilog/cyclonev_hssi
|
||||||
|
cyclonev_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cyclonev_pcie_hip
|
||||||
|
cycloneiv_ver = $MODEL_TECH/../altera/verilog/cycloneiv
|
||||||
|
cycloneiv_hssi_ver = $MODEL_TECH/../altera/verilog/cycloneiv_hssi
|
||||||
|
cycloneiv_pcie_hip_ver = $MODEL_TECH/../altera/verilog/cycloneiv_pcie_hip
|
||||||
|
cycloneive_ver = $MODEL_TECH/../altera/verilog/cycloneive
|
||||||
|
twentynm_ver = $MODEL_TECH/../altera/verilog/twentynm
|
||||||
|
twentynm_hssi_ver = $MODEL_TECH/../altera/verilog/twentynm_hssi
|
||||||
|
twentynm_hip_ver = $MODEL_TECH/../altera/verilog/twentynm_hip
|
||||||
|
cyclone10lp_ver = $MODEL_TECH/../altera/verilog/cyclone10lp
|
||||||
|
|
||||||
|
work = work
|
||||||
|
[vcom]
|
||||||
|
; VHDL93 variable selects language version as the default.
|
||||||
|
; Default is VHDL-2002.
|
||||||
|
; Value of 0 or 1987 for VHDL-1987.
|
||||||
|
; Value of 1 or 1993 for VHDL-1993.
|
||||||
|
; Default or value of 2 or 2002 for VHDL-2002.
|
||||||
|
; Default or value of 3 or 2008 for VHDL-2008.
|
||||||
|
VHDL93 = 2002
|
||||||
|
|
||||||
|
; Show source line containing error. Default is off.
|
||||||
|
; Show_source = 1
|
||||||
|
|
||||||
|
; Turn off unbound-component warnings. Default is on.
|
||||||
|
; Show_Warning1 = 0
|
||||||
|
|
||||||
|
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||||
|
; Show_Warning2 = 0
|
||||||
|
|
||||||
|
; Turn off null-range warnings. Default is on.
|
||||||
|
; Show_Warning3 = 0
|
||||||
|
|
||||||
|
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||||
|
; Show_Warning4 = 0
|
||||||
|
|
||||||
|
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||||
|
; Show_Warning5 = 0
|
||||||
|
|
||||||
|
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||||
|
; Optimize_1164 = 0
|
||||||
|
|
||||||
|
; Turn on resolving of ambiguous function overloading in favor of the
|
||||||
|
; "explicit" function declaration (not the one automatically created by
|
||||||
|
; the compiler for each type declaration). Default is off.
|
||||||
|
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||||
|
; will match the behavior of synthesis tools.
|
||||||
|
Explicit = 1
|
||||||
|
|
||||||
|
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||||
|
; NoVital = 1
|
||||||
|
|
||||||
|
; Turn off VITAL compliance checking. Default is checking on.
|
||||||
|
; NoVitalCheck = 1
|
||||||
|
|
||||||
|
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||||
|
; IgnoreVitalErrors = 1
|
||||||
|
|
||||||
|
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||||
|
; Show_VitalChecksWarnings = 0
|
||||||
|
|
||||||
|
; Keep silent about case statement static warnings.
|
||||||
|
; Default is to give a warning.
|
||||||
|
; NoCaseStaticError = 1
|
||||||
|
|
||||||
|
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||||
|
; Default is to give a warning.
|
||||||
|
; NoOthersStaticError = 1
|
||||||
|
|
||||||
|
; Turn off inclusion of debugging info within design units.
|
||||||
|
; Default is to include debugging info.
|
||||||
|
; NoDebug = 1
|
||||||
|
|
||||||
|
; Turn off "Loading..." messages. Default is messages on.
|
||||||
|
; Quiet = 1
|
||||||
|
|
||||||
|
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||||
|
; -- signals used (read) by a process must be in the sensitivity list
|
||||||
|
; CheckSynthesis = 1
|
||||||
|
|
||||||
|
; Activate optimizations on expressions that do not involve signals,
|
||||||
|
; waits, or function/procedure/task invocations. Default is off.
|
||||||
|
; ScalarOpts = 1
|
||||||
|
|
||||||
|
; Require the user to specify a configuration for all bindings,
|
||||||
|
; and do not generate a compile time default binding for the
|
||||||
|
; component. This will result in an elaboration error of
|
||||||
|
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||||
|
; issue of a false dependency upon the unused default binding.
|
||||||
|
; RequireConfigForAllDefaultBinding = 1
|
||||||
|
|
||||||
|
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||||
|
; scalars defined with subtypes is inhibited by default.
|
||||||
|
; NoIndexCheck = 1
|
||||||
|
|
||||||
|
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||||
|
; scalar objects defined with subtypes.
|
||||||
|
; NoRangeCheck = 1
|
||||||
|
|
||||||
|
[vlog]
|
||||||
|
|
||||||
|
; Turn off inclusion of debugging info within design units.
|
||||||
|
; Default is to include debugging info.
|
||||||
|
; NoDebug = 1
|
||||||
|
|
||||||
|
; Turn off "loading..." messages. Default is messages on.
|
||||||
|
; Quiet = 1
|
||||||
|
|
||||||
|
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||||
|
; Default is off.
|
||||||
|
; Hazard = 1
|
||||||
|
|
||||||
|
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||||
|
; insensitivity for module names. Default is no conversion.
|
||||||
|
; UpCase = 1
|
||||||
|
|
||||||
|
; Turn on incremental compilation of modules. Default is off.
|
||||||
|
; Incremental = 1
|
||||||
|
|
||||||
|
; Turns on lint-style checking.
|
||||||
|
; Show_Lint = 1
|
||||||
|
|
||||||
|
[vsim]
|
||||||
|
; Simulator resolution
|
||||||
|
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||||
|
Resolution = ps
|
||||||
|
|
||||||
|
; User time unit for run commands
|
||||||
|
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||||
|
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||||
|
; then UserTimeUnit defaults to ps.
|
||||||
|
; Should generally be set to default.
|
||||||
|
UserTimeUnit = default
|
||||||
|
|
||||||
|
; Default run length
|
||||||
|
RunLength = 100 ns
|
||||||
|
|
||||||
|
; Maximum iterations that can be run without advancing simulation time
|
||||||
|
IterationLimit = 5000
|
||||||
|
|
||||||
|
; Directive to license manager:
|
||||||
|
; vhdl Immediately reserve a VHDL license
|
||||||
|
; vlog Immediately reserve a Verilog license
|
||||||
|
; plus Immediately reserve a VHDL and Verilog license
|
||||||
|
; nomgc Do not look for Mentor Graphics Licenses
|
||||||
|
; nomti Do not look for Model Technology Licenses
|
||||||
|
; noqueue Do not wait in the license queue when a license isn't available
|
||||||
|
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||||
|
; of queuing for viewer license
|
||||||
|
; License = plus
|
||||||
|
|
||||||
|
; Stop the simulator after a VHDL/Verilog assertion message
|
||||||
|
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||||
|
BreakOnAssertion = 3
|
||||||
|
|
||||||
|
; Assertion Message Format
|
||||||
|
; %S - Severity Level
|
||||||
|
; %R - Report Message
|
||||||
|
; %T - Time of assertion
|
||||||
|
; %D - Delta
|
||||||
|
; %I - Instance or Region pathname (if available)
|
||||||
|
; %% - print '%' character
|
||||||
|
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||||
|
|
||||||
|
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||||
|
; AssertFile = assert.log
|
||||||
|
|
||||||
|
; Default radix for all windows and commands...
|
||||||
|
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||||
|
DefaultRadix = symbolic
|
||||||
|
|
||||||
|
; VSIM Startup command
|
||||||
|
; Startup = do startup.do
|
||||||
|
|
||||||
|
; File for saving command transcript
|
||||||
|
TranscriptFile = transcript
|
||||||
|
|
||||||
|
; File for saving command history
|
||||||
|
; CommandHistory = cmdhist.log
|
||||||
|
|
||||||
|
; Specify whether paths in simulator commands should be described
|
||||||
|
; in VHDL or Verilog format.
|
||||||
|
; For VHDL, PathSeparator = /
|
||||||
|
; For Verilog, PathSeparator = .
|
||||||
|
; Must not be the same character as DatasetSeparator.
|
||||||
|
PathSeparator = /
|
||||||
|
|
||||||
|
; Specify the dataset separator for fully rooted contexts.
|
||||||
|
; The default is ':'. For example, sim:/top
|
||||||
|
; Must not be the same character as PathSeparator.
|
||||||
|
DatasetSeparator = :
|
||||||
|
|
||||||
|
; Disable VHDL assertion messages
|
||||||
|
; IgnoreNote = 1
|
||||||
|
; IgnoreWarning = 1
|
||||||
|
; IgnoreError = 1
|
||||||
|
; IgnoreFailure = 1
|
||||||
|
|
||||||
|
; Default force kind. May be freeze, drive, deposit, or default
|
||||||
|
; or in other terms, fixed, wired, or charged.
|
||||||
|
; A value of "default" will use the signal kind to determine the
|
||||||
|
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||||
|
; DefaultForceKind = freeze
|
||||||
|
|
||||||
|
; If zero, open files when elaborated; otherwise, open files on
|
||||||
|
; first read or write. Default is 0.
|
||||||
|
; DelayFileOpen = 1
|
||||||
|
|
||||||
|
; Control VHDL files opened for write.
|
||||||
|
; 0 = Buffered, 1 = Unbuffered
|
||||||
|
UnbufferedOutput = 0
|
||||||
|
|
||||||
|
; Control the number of VHDL files open concurrently.
|
||||||
|
; This number should always be less than the current ulimit
|
||||||
|
; setting for max file descriptors.
|
||||||
|
; 0 = unlimited
|
||||||
|
ConcurrentFileLimit = 40
|
||||||
|
|
||||||
|
; Control the number of hierarchical regions displayed as
|
||||||
|
; part of a signal name shown in the Wave window.
|
||||||
|
; A value of zero tells VSIM to display the full name.
|
||||||
|
; The default is 0.
|
||||||
|
; WaveSignalNameWidth = 0
|
||||||
|
|
||||||
|
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||||
|
; and std_logic_signed packages.
|
||||||
|
; StdArithNoWarnings = 1
|
||||||
|
|
||||||
|
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||||
|
; NumericStdNoWarnings = 1
|
||||||
|
|
||||||
|
; Control the format of the (VHDL) FOR generate statement label
|
||||||
|
; for each iteration. Do not quote it.
|
||||||
|
; The format string here must contain the conversion codes %s and %d,
|
||||||
|
; in that order, and no other conversion codes. The %s represents
|
||||||
|
; the generate_label; the %d represents the generate parameter value
|
||||||
|
; at a particular generate iteration (this is the position number if
|
||||||
|
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||||
|
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||||
|
; Application of the format must result in a unique scope name over all
|
||||||
|
; such names in the design so that name lookup can function properly.
|
||||||
|
; GenerateFormat = %s__%d
|
||||||
|
|
||||||
|
; Specify whether checkpoint files should be compressed.
|
||||||
|
; The default is 1 (compressed).
|
||||||
|
; CheckpointCompressMode = 0
|
||||||
|
|
||||||
|
; List of dynamically loaded objects for Verilog PLI applications
|
||||||
|
; Veriuser = veriuser.sl
|
||||||
|
|
||||||
|
; Specify default options for the restart command. Options can be one
|
||||||
|
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||||
|
; DefaultRestartOptions = -force
|
||||||
|
|
||||||
|
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||||
|
; (> 500 megabyte memory footprint). Default is disabled.
|
||||||
|
; Specify number of megabytes to lock.
|
||||||
|
; LockedMemory = 1000
|
||||||
|
|
||||||
|
; Turn on (1) or off (0) WLF file compression.
|
||||||
|
; The default is 1 (compress WLF file).
|
||||||
|
; WLFCompress = 0
|
||||||
|
|
||||||
|
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||||
|
; or only regions containing logged signals (0).
|
||||||
|
; The default is 0 (save only regions with logged signals).
|
||||||
|
; WLFSaveAllRegions = 1
|
||||||
|
|
||||||
|
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||||
|
; to the specified amount of simulation time. When the limit is exceeded
|
||||||
|
; the earliest times get truncated from the file.
|
||||||
|
; If both time and size limits are specified the most restrictive is used.
|
||||||
|
; UserTimeUnits are used if time units are not specified.
|
||||||
|
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||||
|
; WLFTimeLimit = 0
|
||||||
|
|
||||||
|
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||||
|
; to the specified number of megabytes. If both time and size limits
|
||||||
|
; are specified then the most restrictive is used.
|
||||||
|
; The default is 0 (no limit).
|
||||||
|
; WLFSizeLimit = 1000
|
||||||
|
|
||||||
|
; Specify whether or not a WLF file should be deleted when the
|
||||||
|
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||||
|
; The default is 0 (do not delete WLF file when simulation ends).
|
||||||
|
; WLFDeleteOnQuit = 1
|
||||||
|
|
||||||
|
; Automatic SDF compilation
|
||||||
|
; Disables automatic compilation of SDF files in flows that support it.
|
||||||
|
; Default is on, uncomment to turn off.
|
||||||
|
; NoAutoSDFCompile = 1
|
||||||
|
|
||||||
|
[lmc]
|
||||||
|
|
||||||
|
[msg_system]
|
||||||
|
suppress = 3116
|
||||||
|
; Change a message severity or suppress a message.
|
||||||
|
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||||
|
; Examples:
|
||||||
|
; note = 3009
|
||||||
|
; warning = 3033
|
||||||
|
; error = 3010,3016
|
||||||
|
; fatal = 3016,3033
|
||||||
|
; suppress = 3009,3016,3043
|
||||||
|
; The command verror <msg number> can be used to get the complete
|
||||||
|
; description of a message.
|
||||||
|
|
||||||
|
; Control transcripting of elaboration/runtime messages.
|
||||||
|
; The default is to have messages appear in the transcript and
|
||||||
|
; recorded in the wlf file (messages that are recorded in the
|
||||||
|
; wlf file can be viewed in the MsgViewer). The other settings
|
||||||
|
; are to send messages only to the transcript or only to the
|
||||||
|
; wlf file. The valid values are
|
||||||
|
; both {default}
|
||||||
|
; tran {transcript only}
|
||||||
|
; wlf {wlf file only}
|
||||||
|
; msgmode = both
|
||||||
|
[Project]
|
||||||
|
** Warning: ; Warning -- Do not edit the project properties directly.
|
||||||
|
; Property names are dynamic in nature and property
|
||||||
|
; values have special syntax. Changing property data directly
|
||||||
|
; can result in a corrupt MPF file. All project properties
|
||||||
|
; can be modified through project window dialogs.
|
||||||
|
Project_Version = 6
|
||||||
|
Project_DefaultLib = work
|
||||||
|
Project_SortMethod = unused
|
||||||
|
Project_Files_Count = 2
|
||||||
|
Project_File_0 = /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v
|
||||||
|
Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1652793275 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
|
||||||
|
Project_File_1 = /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v
|
||||||
|
Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652794988 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
|
||||||
|
Project_Sim_Count = 1
|
||||||
|
Project_Sim_0 = Simulation 1
|
||||||
|
Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_7_testbench folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {}
|
||||||
|
Project_Folder_Count = 0
|
||||||
|
Echo_Compile_Output = 0
|
||||||
|
Save_Compile_Report = 1
|
||||||
|
Project_Opt_Count = 0
|
||||||
|
ForceSoftPaths = 0
|
||||||
|
ProjectStatusDelay = 5000
|
||||||
|
VERILOG_DoubleClick = Edit
|
||||||
|
VERILOG_CustomDoubleClick =
|
||||||
|
SYSTEMVERILOG_DoubleClick = Edit
|
||||||
|
SYSTEMVERILOG_CustomDoubleClick =
|
||||||
|
VHDL_DoubleClick = Edit
|
||||||
|
VHDL_CustomDoubleClick =
|
||||||
|
PSL_DoubleClick = Edit
|
||||||
|
PSL_CustomDoubleClick =
|
||||||
|
TEXT_DoubleClick = Edit
|
||||||
|
TEXT_CustomDoubleClick =
|
||||||
|
SYSTEMC_DoubleClick = Edit
|
||||||
|
SYSTEMC_CustomDoubleClick =
|
||||||
|
TCL_DoubleClick = Edit
|
||||||
|
TCL_CustomDoubleClick =
|
||||||
|
MACRO_DoubleClick = Edit
|
||||||
|
MACRO_CustomDoubleClick =
|
||||||
|
VCD_DoubleClick = Edit
|
||||||
|
VCD_CustomDoubleClick =
|
||||||
|
SDF_DoubleClick = Edit
|
||||||
|
SDF_CustomDoubleClick =
|
||||||
|
XML_DoubleClick = Edit
|
||||||
|
XML_CustomDoubleClick =
|
||||||
|
LOGFILE_DoubleClick = Edit
|
||||||
|
LOGFILE_CustomDoubleClick =
|
||||||
|
UCDB_DoubleClick = Edit
|
||||||
|
UCDB_CustomDoubleClick =
|
||||||
|
TDB_DoubleClick = Edit
|
||||||
|
TDB_CustomDoubleClick =
|
||||||
|
UPF_DoubleClick = Edit
|
||||||
|
UPF_CustomDoubleClick =
|
||||||
|
PCF_DoubleClick = Edit
|
||||||
|
PCF_CustomDoubleClick =
|
||||||
|
PROJECT_DoubleClick = Edit
|
||||||
|
PROJECT_CustomDoubleClick =
|
||||||
|
VRM_DoubleClick = Edit
|
||||||
|
VRM_CustomDoubleClick =
|
||||||
|
DEBUGDATABASE_DoubleClick = Edit
|
||||||
|
DEBUGDATABASE_CustomDoubleClick =
|
||||||
|
DEBUGARCHIVE_DoubleClick = Edit
|
||||||
|
DEBUGARCHIVE_CustomDoubleClick =
|
||||||
|
Project_Major_Version = 2020
|
||||||
|
Project_Minor_Version = 1
|
||||||
13
Quartus/v7_testbench/transcript
Normal file
13
Quartus/v7_testbench/transcript
Normal file
|
|
@ -0,0 +1,13 @@
|
||||||
|
# Compile of jyh_4490_7_testbench.v was successful.
|
||||||
|
vsim work.jyh_4490_7_testbench
|
||||||
|
# vsim work.jyh_4490_7_testbench
|
||||||
|
# Start time: 21:43:41 on May 17,2022
|
||||||
|
# Loading work.jyh_4490_7_testbench
|
||||||
|
# Loading work.jyh_4490_7_is
|
||||||
|
add wave -position end sim:/jyh_4490_7_testbench/clk
|
||||||
|
add wave -position end sim:/jyh_4490_7_testbench/f0
|
||||||
|
add wave -position end sim:/jyh_4490_7_testbench/f1
|
||||||
|
add wave -position end sim:/jyh_4490_7_testbench/f2
|
||||||
|
add wave -position end sim:/jyh_4490_7_testbench/p
|
||||||
|
add wave -position end sim:/jyh_4490_7_testbench/sta
|
||||||
|
run -all
|
||||||
57
Quartus/v7_testbench/work/_info
Normal file
57
Quartus/v7_testbench/work/_info
Normal file
|
|
@ -0,0 +1,57 @@
|
||||||
|
m255
|
||||||
|
K4
|
||||||
|
z2
|
||||||
|
!s11f vlog 2020.1 2020.02, Feb 28 2020
|
||||||
|
13
|
||||||
|
!s112 1.1
|
||||||
|
!i10d 8192
|
||||||
|
!i10e 25
|
||||||
|
!i10f 100
|
||||||
|
cModel Technology
|
||||||
|
d/home/ir
|
||||||
|
vjyh_4490_7_is
|
||||||
|
!s110 1652794566
|
||||||
|
!i10b 1
|
||||||
|
!s100 Ch8NYc=4G@_6A9YaMMBnW2
|
||||||
|
Z0 !s11b Dg1SIo80bB@j0V0VzS_@n1
|
||||||
|
IBT5^kcKVcE01P1:cX?C;^2
|
||||||
|
Z1 VDg1SIo80bB@j0V0VzS_@n1
|
||||||
|
Z2 d/home/ir/Documents/codelib/Quartus/v7_testbench
|
||||||
|
w1652793275
|
||||||
|
8/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v
|
||||||
|
F/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v
|
||||||
|
!i122 0
|
||||||
|
L0 1 79
|
||||||
|
Z3 OV;L;2020.1;71
|
||||||
|
r1
|
||||||
|
!s85 0
|
||||||
|
31
|
||||||
|
!s108 1652794566.000000
|
||||||
|
!s107 /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v|
|
||||||
|
!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_is.v|
|
||||||
|
!i113 1
|
||||||
|
Z4 o-work work
|
||||||
|
Z5 tCvgOpt 0
|
||||||
|
vjyh_4490_7_testbench
|
||||||
|
!s110 1652795018
|
||||||
|
!i10b 1
|
||||||
|
!s100 GcKJLC2lo5LW?eghjQ?C61
|
||||||
|
R0
|
||||||
|
Id=?e<lcL3XT8`OM]nNcha3
|
||||||
|
R1
|
||||||
|
R2
|
||||||
|
w1652794988
|
||||||
|
8/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v
|
||||||
|
F/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v
|
||||||
|
!i122 2
|
||||||
|
L0 2 60
|
||||||
|
R3
|
||||||
|
r1
|
||||||
|
!s85 0
|
||||||
|
31
|
||||||
|
!s108 1652795018.000000
|
||||||
|
!s107 /home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v|
|
||||||
|
!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v7/jyh_4490_7_testbench.v|
|
||||||
|
!i113 1
|
||||||
|
R4
|
||||||
|
R5
|
||||||
BIN
Quartus/v7_testbench/work/_lib1_0.qpg
Normal file
BIN
Quartus/v7_testbench/work/_lib1_0.qpg
Normal file
Binary file not shown.
4
Quartus/v7_testbench/work/_vmake
Normal file
4
Quartus/v7_testbench/work/_vmake
Normal file
|
|
@ -0,0 +1,4 @@
|
||||||
|
m255
|
||||||
|
K4
|
||||||
|
z0
|
||||||
|
cModel Technology
|
||||||
Reference in a new issue