From d9dab07172c4d03905b9cff93d3ae173b2c72c16 Mon Sep 17 00:00:00 2001 From: iridiumR Date: Wed, 30 Mar 2022 11:54:07 +0800 Subject: [PATCH] =?UTF-8?q?=E6=95=B0=E7=94=B5=E5=AE=9E=E9=AA=8C=E7=AC=AC?= =?UTF-8?q?=E4=B8=80=E6=AC=A1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Quartus/v1/Waveform.vwf | 465 ++++++++++++++++++++++++++++++++++++++ Quartus/v1/jyh_4490_1.qsf | 8 +- Quartus/v1/jyh_4490_1.v | 23 ++ 3 files changed, 495 insertions(+), 1 deletion(-) create mode 100644 Quartus/v1/Waveform.vwf create mode 100644 Quartus/v1/jyh_4490_1.v diff --git a/Quartus/v1/Waveform.vwf b/Quartus/v1/Waveform.vwf new file mode 100644 index 0000000..c72fa3d --- /dev/null +++ b/Quartus/v1/Waveform.vwf @@ -0,0 +1,465 @@ +/* +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_1 -c jyh_4490_1 --vector_source="/home/ir/Documents/codelib/Quartus/v1/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/Waveform.vwf.vt" +quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off jyh_4490_1 -c jyh_4490_1 --vector_source="/home/ir/Documents/codelib/Quartus/v1/Waveform.vwf" --testbench_file="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/Waveform.vwf.vt" +quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/" jyh_4490_1 -c jyh_4490_1 +quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/ir/Documents/codelib/Quartus/v1/simulation/qsim/" jyh_4490_1 -c jyh_4490_1 +onerror {exit -code 1} +vlib work +vlog -work work jyh_4490_1.vo +vlog -work work Waveform.vwf.vt +vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_1_vlg_vec_tst +vcd file -direction jyh_4490_1.msim.vcd +vcd add -internal jyh_4490_1_vlg_vec_tst/* +vcd add -internal jyh_4490_1_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +onerror {exit -code 1} +vlib work +vlog -work work jyh_4490_1.vo +vlog -work work Waveform.vwf.vt +vsim -novopt -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.jyh_4490_1_vlg_vec_tst +vcd file -direction jyh_4490_1.msim.vcd +vcd add -internal jyh_4490_1_vlg_vec_tst/* +vcd add -internal jyh_4490_1_vlg_vec_tst/i1/* +proc simTimestamp {} { + echo "Simulation time: $::now ps" + if { [string equal running [runStatus]] } { + after 2500 simTimestamp + } +} +after 2500 simTimestamp +run -all +quit -f + +verilog +*/ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 2021 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("codeout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 7; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("codeout[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "codeout"; +} + +SIGNAL("codeout[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "codeout"; +} + +SIGNAL("codeout[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "codeout"; +} + +SIGNAL("codeout[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "codeout"; +} + +SIGNAL("codeout[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "codeout"; +} + +SIGNAL("codeout[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "codeout"; +} + +SIGNAL("codeout[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "codeout"; +} + +SIGNAL("indec") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 4; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("indec[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "indec"; +} + +SIGNAL("indec[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "indec"; +} + +SIGNAL("indec[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "indec"; +} + +SIGNAL("indec[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "indec"; +} + +TRANSITION_LIST("codeout[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("codeout[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("codeout[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("codeout[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("codeout[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("codeout[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("codeout[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("indec[3]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 6; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + } + LEVEL 0 FOR 40.0; + } +} + +TRANSITION_LIST("indec[2]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 12; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + } + LEVEL 0 FOR 40.0; + } +} + +TRANSITION_LIST("indec[1]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 25; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } + } +} + +TRANSITION_LIST("indec[0]") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 50; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + } + } +} + +DISPLAY_LINE +{ + CHANNEL = "indec"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; + CHILDREN = 1, 2, 3, 4; +} + +DISPLAY_LINE +{ + CHANNEL = "indec[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "indec[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "indec[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "indec[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout"; + EXPAND_STATUS = EXPANDED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 0; + CHILDREN = 6, 7, 8, 9, 10, 11, 12; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 5; +} + +DISPLAY_LINE +{ + CHANNEL = "codeout[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 5; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/Quartus/v1/jyh_4490_1.qsf b/Quartus/v1/jyh_4490_1.qsf index 43d6328..13e6bbc 100644 --- a/Quartus/v1/jyh_4490_1.qsf +++ b/Quartus/v1/jyh_4490_1.qsf @@ -48,4 +48,10 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V \ No newline at end of file +set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V +set_global_assignment -name VERILOG_FILE jyh_4490_1.v +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/v1/jyh_4490_1.v b/Quartus/v1/jyh_4490_1.v new file mode 100644 index 0000000..41bea82 --- /dev/null +++ b/Quartus/v1/jyh_4490_1.v @@ -0,0 +1,23 @@ +module jyh_4490_1(codeout,indec); + input[3:0] indec; + output[6:0] codeout; + + reg[6:0] codeout; + +always @ (indec) + begin + case (indec) + 4'd0: codeout=7'b1111110; + 4'd1: codeout=7'b0110000; + 4'd2: codeout=7'b1101101; + 4'd3: codeout=7'b1111001; + 4'd4: codeout=7'b0110011; + 4'd5: codeout=7'b1011011; + 4'd6: codeout=7'b1011111; + 4'd7: codeout=7'b1110000; + 4'd8: codeout=7'b1111111; + 4'd9: codeout=7'b1111011; + default: codeout=7'bx; + endcase + end +endmodule \ No newline at end of file