diff --git a/Quartus/v6/jyh_4490_6.qsf b/Quartus/v6/jyh_4490_6.qsf index c759d36..e76be9e 100644 --- a/Quartus/v6/jyh_4490_6.qsf +++ b/Quartus/v6/jyh_4490_6.qsf @@ -54,9 +54,32 @@ set_global_assignment -name VERILOG_FILE jyh_4490_6_counter.v set_global_assignment -name VERILOG_FILE jyh_4490_6_encoder.v set_global_assignment -name VERILOG_FILE jyh_4490_6_entry.v set_global_assignment -name VERILOG_FILE jyh_4490_6_testbench_top.v +set_global_assignment -name VERILOG_FILE jyh_4490_6_divider.v +set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf +set_location_assignment PIN_90 -to clk_50m +set_location_assignment PIN_100 -to code[5] +set_location_assignment PIN_112 -to code[6] +set_location_assignment PIN_104 -to code[4] +set_location_assignment PIN_111 -to code[3] +set_location_assignment PIN_106 -to code[2] +set_location_assignment PIN_110 -to code[1] +set_location_assignment PIN_103 -to code[0] +set_location_assignment PIN_31 -to en +set_location_assignment PIN_30 -to in +set_location_assignment PIN_54 -to out0[3] +set_location_assignment PIN_52 -to out0[2] +set_location_assignment PIN_50 -to out0[1] +set_location_assignment PIN_46 -to out0[0] +set_location_assignment PIN_119 -to seg[7] +set_location_assignment PIN_126 -to seg[6] +set_location_assignment PIN_115 -to seg[5] +set_location_assignment PIN_125 -to seg[4] +set_location_assignment PIN_114 -to seg[3] +set_location_assignment PIN_121 -to seg[2] +set_location_assignment PIN_113 -to seg[1] +set_location_assignment PIN_120 -to seg[0] +set_location_assignment PIN_33 -to subclk set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name VERILOG_FILE jyh_4490_6_divider.v -set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/Quartus/v6/jyh_4490_6_entry.v b/Quartus/v6/jyh_4490_6_entry.v index 0923729..ac39cde 100644 --- a/Quartus/v6/jyh_4490_6_entry.v +++ b/Quartus/v6/jyh_4490_6_entry.v @@ -1,13 +1,14 @@ module jyh_4490_6_entry(code, seg, clk_50m, en, in, //数码管型码 数码管位码 50M 使能信号 按键 - out0, subclk); - //计数值 消抖值 + out0, cnt, subclk); + //计数值 消抖值 output [6:0] code; output [7:0] seg; input en,clk_50m,in; output subclk; output [3:0] out0; +output [19:0] cnt; wire freshclk; @@ -44,6 +45,7 @@ jyh_4490_mstate M1( .clk(clk_50m), .in(in), .en(en), -.out(subclk) +.out(subclk), +.cnt(cnt) ); endmodule diff --git a/Quartus/v6/jyh_4490_6_testbench_top.v b/Quartus/v6/jyh_4490_6_testbench_top.v index d6ccaf5..bbb68a4 100644 --- a/Quartus/v6/jyh_4490_6_testbench_top.v +++ b/Quartus/v6/jyh_4490_6_testbench_top.v @@ -18,8 +18,8 @@ end always#10 clk=~clk; always begin + #1500000; in=0; - #15000000; repeat(5) begin in=1; @@ -28,7 +28,7 @@ begin #1000000; end in=1; - #30000000; + #35000000 repeat(5) begin in=0; @@ -40,8 +40,10 @@ begin #15000000; end + jyh_4490_6_entry E1(.code(code),.seg(seg),.clk_50m(clk),.en(en),.in(in), //数码管型码 数码管位码 50M 清零信号 使能信号 按键 - .out0(out0),.subclk(subclk)); + .out0(out0),.subclk(subclk),.cnt(cnt)); + //计数值 消抖值 endmodule \ No newline at end of file diff --git a/Quartus/v6_testbench/jyh_4490_6.cr.mti b/Quartus/v6_testbench/jyh_4490_6.cr.mti index 64aba45..db15be1 100644 --- a/Quartus/v6_testbench/jyh_4490_6.cr.mti +++ b/Quartus/v6_testbench/jyh_4490_6.cr.mti @@ -1,4 +1,11 @@ -/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v +/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module jyh_4490_6_testbench + +Top level modules: + jyh_4490_6_testbench + +} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module jyh_4490_mstate diff --git a/Quartus/v6_testbench/transcript b/Quartus/v6_testbench/transcript index 808c0d2..aeb82df 100644 --- a/Quartus/v6_testbench/transcript +++ b/Quartus/v6_testbench/transcript @@ -14,3 +14,7 @@ add wave -position end sim:/jyh_4490_6_testbench/out add wave -position end sim:/jyh_4490_6_testbench/cnt run -continue run -all +# Break key hit +# Simulation stop requested. +# End time: 18:28:16 on May 10,2022, Elapsed time: 0:22:17 +# Errors: 0, Warnings: 6 diff --git a/Quartus/v6_testbench_top/jyh_4490_top.cr.mti b/Quartus/v6_testbench_top/jyh_4490_top.cr.mti index b6d1dcc..90d3a74 100644 --- a/Quartus/v6_testbench_top/jyh_4490_top.cr.mti +++ b/Quartus/v6_testbench_top/jyh_4490_top.cr.mti @@ -19,6 +19,13 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb Top level modules: jyh_4490_4_encoder +} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v +Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 +-- Compiling module jyh_4490_6_testbench + +Top level modules: + jyh_4490_6_testbench + } {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 -- Compiling module jyh_4490_mstate @@ -26,18 +33,4 @@ Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb Top level modules: jyh_4490_mstate -} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v -Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 --- Compiling module jyh_4490_6_entry - -Top level modules: - jyh_4490_6_entry - -} {} {}} /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v {1 {vlog -work work -stats=none /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v -Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 --- Compiling module jyh_4490_6_testbench_top - -Top level modules: - jyh_4490_6_testbench_top - } {} {}} diff --git a/Quartus/v6_testbench_top/jyh_4490_top.mpf b/Quartus/v6_testbench_top/jyh_4490_top.mpf index 4b8709b..acf8ec9 100644 --- a/Quartus/v6_testbench_top/jyh_4490_top.mpf +++ b/Quartus/v6_testbench_top/jyh_4490_top.mpf @@ -411,22 +411,24 @@ suppress = 3116 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 6 +Project_Files_Count = 7 Project_File_0 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v -Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1652174341 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_1 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v -Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1652170623 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_2 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v -Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1652175670 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0 -Project_File_3 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v -Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1652112350 cover_fsm 0 cover_branch 0 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 -Project_File_4 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v -Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 last_compile 1652176054 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_0 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652174341 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_1 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v +Project_File_P_1 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652175670 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_2 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v +Project_File_P_2 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652170623 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_3 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v +Project_File_P_3 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652177049 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0 +Project_File_4 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v +Project_File_P_4 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652112350 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 vlog_showsource 0 vlog_hazard 0 cover_optlevel 3 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0 Project_File_5 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v -Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 folder {Top Level} last_compile 1652176229 cover_fsm 0 cover_branch 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_P_5 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652240573 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0 +Project_File_6 = /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v +Project_File_P_6 = cover_toggle 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 folder {Top Level} last_compile 1652240785 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 cover_optlevel 3 vlog_hazard 0 vlog_showsource 0 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0 Project_Sim_Count = 1 Project_Sim_0 = Simulation 1 -Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_6_testbench_top folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 0 is_vopt_flow 0 Generics {} +Project_Sim_P_0 = -L {} -Lf {} -sdf {} selected_du {} additional_dus work.jyh_4490_6_testbench_top folder {Top Level} ok 1 -t default timing default +plusarg {} -nofileshare 0 -sdfnowarn 0 -wlf {} OtherArgs {} -coverage 0 -sdfnoerror 0 -std_input {} -hazards 0 -noglitch 0 -absentisempty 0 +no_pulse_msg 0 -sc22 0 +pulse_r {} -assertfile {} -multisource_delay {} -vital2.2b 0 +notimingchecks 0 +pulse_e {} -std_output {} vopt_env 1 is_vopt_flow 0 Generics {} Project_Folder_Count = 0 Echo_Compile_Output = 0 Save_Compile_Report = 1 diff --git a/Quartus/v6_testbench_top/transcript b/Quartus/v6_testbench_top/transcript index 431ac66..4007621 100644 --- a/Quartus/v6_testbench_top/transcript +++ b/Quartus/v6_testbench_top/transcript @@ -1,24 +1,33 @@ +# Compile of jyh_4490_6_counter.v was successful. +# Compile of jyh_4490_6_divider.v was successful. +# Compile of jyh_4490_6_encoder.v was successful. # Compile of jyh_4490_6_entry.v was successful. +# Compile of jyh_4490_6_testbench.v was successful. +# Compile of jyh_4490_6_testbench_top.v failed with 2 errors. +# Compile of jyh_4490_mstate.v was successful. +# 7 compiles, 1 failed with 2 errors. +# Compile of jyh_4490_6_testbench_top.v was successful. vsim work.jyh_4490_6_testbench_top # vsim work.jyh_4490_6_testbench_top -# Start time: 17:50:53 on May 10,2022 +# Start time: 11:46:34 on May 11,2022 # Loading work.jyh_4490_6_testbench_top # Loading work.jyh_4490_6_entry # Loading work.jyh_4490_6_divider # Loading work.jyh_4490_6_counter # Loading work.jyh_4490_4_encoder +# Loading work.jyh_4490_mstate # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'C1'. Expected 7, found 4. -# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/C1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 28 -# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'load'. -# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'in'. -# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'co'. +# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/C1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 29 +# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(29): [TFMPC] - Missing connection for port 'load'. +# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(29): [TFMPC] - Missing connection for port 'in'. +# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(29): [TFMPC] - Missing connection for port 'co'. # ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'E1'. Expected 7, found 4. -# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 35 +# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 36 # ** Warning: (vsim-3015) [PCDPC] - Port size (7) does not match connection size (4) for port 'd1'. The port definition is at: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v(2). -# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 35 -# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd2'. -# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd3'. -# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd4'. +# Time: 0 ns Iteration: 0 Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 36 +# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(36): [TFMPC] - Missing connection for port 'd2'. +# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(36): [TFMPC] - Missing connection for port 'd3'. +# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(36): [TFMPC] - Missing connection for port 'd4'. add wave -position end sim:/jyh_4490_6_testbench_top/clk add wave -position end sim:/jyh_4490_6_testbench_top/code add wave -position end sim:/jyh_4490_6_testbench_top/seg @@ -28,6 +37,3 @@ add wave -position end sim:/jyh_4490_6_testbench_top/en add wave -position end sim:/jyh_4490_6_testbench_top/subclk add wave -position end sim:/jyh_4490_6_testbench_top/out0 run -all -# Break key hit -# Closing project /home/ir/Documents/codelib/Quartus/v6_testbench_top/jyh_4490_top.mpf -# Simulation stop requested. diff --git a/Quartus/v6_testbench_top/work/_info b/Quartus/v6_testbench_top/work/_info index a0f7315..218c8b1 100644 --- a/Quartus/v6_testbench_top/work/_info +++ b/Quartus/v6_testbench_top/work/_info @@ -10,7 +10,7 @@ z2 cModel Technology d/home/ir vjyh_4490_4_encoder -Z0 !s110 1652176119 +Z0 !s110 1652240689 !i10b 1 !s100 cFk5FR?`]C?]?DGkTnFdM3 Z1 !s11b Dg1SIo80bB@j0V0VzS_@n1 @@ -20,13 +20,13 @@ Z3 d/home/ir/Documents/codelib/Quartus/v6_testbench_top w1652170623 8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v -!i122 32 +!i122 9 L0 2 69 Z4 OV;L;2020.1;71 r1 !s85 0 31 -Z5 !s108 1652176119.000000 +Z5 !s108 1652240689.000000 !s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v| !s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v| !i113 1 @@ -43,7 +43,7 @@ R3 w1652175670 8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_counter.v -!i122 31 +!i122 7 L0 1 63 R4 r1 @@ -66,7 +66,7 @@ R3 w1652174341 8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_divider.v -!i122 35 +!i122 8 L0 1 19 R4 r1 @@ -79,46 +79,69 @@ R5 R6 R7 vjyh_4490_6_entry -!s110 1652176250 -!i10b 1 -!s100 _do]J5iN2 -R1 -If?WILTjA`b0;9mDFQ5c;b3 -R2 -R3 -w1652176229 -8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v -F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v -!i122 36 -L0 1 49 -R4 -r1 -!s85 0 -31 -!s108 1652176250.000000 -!s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v| -!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v| -!i113 1 -R6 -R7 -vjyh_4490_6_testbench_top R0 !i10b 1 -!s100 k9eCo38DPdEAiBM=H[=aN0 +!s100 fDg?`>QF<:IFc6=ZN<7S92 R1 -I45bo^1ZU4HdY1 R2 R3 -w1652176054 -8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v -F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v -!i122 33 -L0 2 46 +w1652240573 +8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v +F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v +!i122 10 +L0 1 51 R4 r1 !s85 0 31 R5 +!s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v| +!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v| +!i113 1 +R6 +R7 +vjyh_4490_6_testbench +R0 +!i10b 1 +!s100 `NfM;beY^i;lN3FJ7YLhn2 +R1 +IUX02=3ELh^jdNI5icO]2<3 +R2 +R3 +w1652177049 +8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v +F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v +!i122 11 +L0 2 45 +R4 +r1 +!s85 0 +31 +R5 +!s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v| +!s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench.v| +!i113 1 +R6 +R7 +vjyh_4490_6_testbench_top +!s110 1652240790 +!i10b 1 +!s100 ?jWEb^A:D0OT7^[jWkZPO2 +R1 +IXd_A3:9mO`z]NBP2U@Wa=0 +R2 +R3 +w1652240785 +8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v +F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v +!i122 14 +L0 2 48 +R4 +r1 +!s85 0 +31 +!s108 1652240790.000000 !s107 /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v| !s90 -reportprogress|300|-work|work|-stats=none|/home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_testbench_top.v| !i113 1 @@ -135,7 +158,7 @@ R3 w1652112350 8/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v F/home/ir/Documents/codelib/Quartus/v6/jyh_4490_mstate.v -!i122 34 +!i122 13 L0 1 53 R4 r1 diff --git a/Quartus/v6_testbench_top/work/_lib1_1.qpg b/Quartus/v6_testbench_top/work/_lib1_0.qpg similarity index 59% rename from Quartus/v6_testbench_top/work/_lib1_1.qpg rename to Quartus/v6_testbench_top/work/_lib1_0.qpg index deeec28..f92d48e 100644 Binary files a/Quartus/v6_testbench_top/work/_lib1_1.qpg and b/Quartus/v6_testbench_top/work/_lib1_0.qpg differ