module jyh_4490_mstate(clk,in,en,out,cnt);
input clk,in,en;
output reg out;
output reg [19:0] cnt=0;
reg[1:0] state=0;
parameter s0=0,s1=1,s2=2,s3=3;
parameter TARGET=750000; //50mhz 15ms

always @(posedge clk)
if(!en)
	state=s0;
else
   case(state)
	s0:
	begin
		out=0;
		cnt=0;
		if(in)
			state=s1;
	end
	s1:
		begin
		out=0;
		if(cnt<TARGET)
		begin
			state=s1;
			cnt=cnt+1;
		end
		else 
			begin
				cnt=0;
			   if(in)
				state=s2;
				else
				state=s0;
			end
		end
	s2:
	begin
		out=1;
		cnt=0;
		if(!in)
			state=s3;
	end
	s3:
		begin
		out=1;
		if(cnt<TARGET)
		begin
			state=s3;
			cnt=cnt+1;
		end
		else 
			begin
				cnt=0;
			   if(in)
				state=s2;
				else
				state=s0;
			end
		end
	default:
	begin
		state=s0;
		out=0;
		cnt=0;
	end
endcase


endmodule