# Compile of jyh_4490_5_divider.v was successful.
vsim work.jyh_4490_5_testbench
# vsim work.jyh_4490_5_testbench 
# Start time: 21:31:49 on Apr 19,2022
# Loading work.jyh_4490_5_testbench
# Loading work.jyh_4490_5_divider
add wave -position end  sim:/jyh_4490_5_testbench/clk
add wave -position end  sim:/jyh_4490_5_testbench/en
add wave -position end  sim:/jyh_4490_5_testbench/sel
add wave -position end  sim:/jyh_4490_5_testbench/clk_out
run -continue
run -all
run