# Compile of jyh_4490_6_entry.v was successful.
vsim work.jyh_4490_6_testbench_top
# vsim work.jyh_4490_6_testbench_top 
# Start time: 17:50:53 on May 10,2022
# Loading work.jyh_4490_6_testbench_top
# Loading work.jyh_4490_6_entry
# Loading work.jyh_4490_6_divider
# Loading work.jyh_4490_6_counter
# Loading work.jyh_4490_4_encoder
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'C1'.  Expected 7, found 4.
#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/C1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 28
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'load'.
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'in'.
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(28): [TFMPC] - Missing connection for port 'co'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'E1'.  Expected 7, found 4.
#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 35
# ** Warning: (vsim-3015) [PCDPC] - Port size (7) does not match connection size (4) for port 'd1'. The port definition is at: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_encoder.v(2).
#    Time: 0 ns  Iteration: 0  Instance: /jyh_4490_6_testbench_top/E1/E1 File: /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v Line: 35
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd2'.
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd3'.
# ** Warning: (vsim-3722) /home/ir/Documents/codelib/Quartus/v6/jyh_4490_6_entry.v(35): [TFMPC] - Missing connection for port 'd4'.
add wave -position end  sim:/jyh_4490_6_testbench_top/clk
add wave -position end  sim:/jyh_4490_6_testbench_top/code
add wave -position end  sim:/jyh_4490_6_testbench_top/seg
add wave -position end  sim:/jyh_4490_6_testbench_top/cnt
add wave -position end  sim:/jyh_4490_6_testbench_top/in
add wave -position end  sim:/jyh_4490_6_testbench_top/en
add wave -position end  sim:/jyh_4490_6_testbench_top/subclk
add wave -position end  sim:/jyh_4490_6_testbench_top/out0
run -all
# Break key hit
# Closing project /home/ir/Documents/codelib/Quartus/v6_testbench_top/jyh_4490_top.mpf
# Simulation stop requested.