`timescale 1ns/1ns
module jyh_4490_6_testbench;
reg clk;
reg in;
reg en;
wire out;
wire [19:0] cnt;

initial begin
	clk=0;
	in=0;
	en=1;
end

always#10 clk=~clk;
always
begin
	#1500000;
	in=0;
	repeat(5)
	begin
		in=1;
		#1000000;
		in=0;
		#1000000;
	end
	in=1;
	#35000000
	repeat(5)
	begin
		in=0;
		#1000000;
		in=1;
		#1000000;
	end
	in=0;
	#15000000;
end
	
jyh_4490_mstate M1(
.clk(clk),
.in(in),
.out(out),
.cnt(cnt));

endmodule