module jyh_4490_7_is(f2,f1,f0,clk,p,sta);
input p,sta,f0,clk;
output reg f2,f1;

reg flag,flag2;//counter enable flag
parameter TARGET=15000; //0.3ms
parameter TARGET2=5000; //0.1ms
reg [13:0] count;//2^14=16384
reg [14:0] count2;//2^15=32768
reg negf0; //whether f0 enter low level
initial begin
flag=0;
flag2=0;
count=0;
negf0=0;
end

always@(posedge clk)
begin
	if(!f0)
		negf0<=1;
	if(f0&&negf0)
	begin
		negf0<=0;
		flag<=1;
		flag2<=1;
		f1<=1;
		f2<=1;
	end
	else
	begin
	  //xinchong
		if(count>=TARGET)
		begin
			flag<=0;
			f1<=0;
		end
		
		//shaochong
		if(p)
			if(sta)
			begin
				if(count>=5*TARGET2)
				begin
					f2<=0;
					flag2<=0;	
					//end of a circle
				end
				else if(count==4*TARGET2)
					f2<=1;
			end
			if(count>=3*TARGET2)
			begin
				f2<=0;
				if(!sta)
					flag2<=0;
					//end of a circle
			end
			else if(count>=2*TARGET2)
				f2<=1;
			else if(count>=TARGET2)
				f2<=0;
		else
			f2<=f1;
	
		
		//whether to add counter
		if(flag)
			count<=count+1;
		else
			count<=0;
		if(flag2)
			count2<=count+1;
		else
			count2<=0;
	end
end

endmodule