`timescale 1ns/1ns
module jyh_4490_7_testbench;
wire f1,f2;
reg clk,f0,p,sta;

initial begin
clk=0;
f0=0;
p=0;
sta=0;
end

always #10 clk=~clk;
always begin    

f0=1;
#30000;
f0=0;
#70000;

f0=1;
#24000;
f0=0;
#76000;

f0=1;
#18000;
f0=0;
#82000;

f0=1;
#12000;
f0=0;
#80000;

f0=1;
#6000; 
f0=0;
#94000;

end

always begin
p=0;
sta=0;
#600000;
p=1;
#300000;
sta=1;
#300000;
end

jyh_4490_7_is C0(
.clk(clk),
.p(p),
.f1(f1),
.f0(f0),
.sta(sta),
.f2(f2));

endmodule