# Compile of jyh_4490_7_testbench.v was successful.
vsim work.jyh_4490_7_testbench
# vsim work.jyh_4490_7_testbench 
# Start time: 21:43:41 on May 17,2022
# Loading work.jyh_4490_7_testbench
# Loading work.jyh_4490_7_is
add wave -position end  sim:/jyh_4490_7_testbench/clk
add wave -position end  sim:/jyh_4490_7_testbench/f0
add wave -position end  sim:/jyh_4490_7_testbench/f1
add wave -position end  sim:/jyh_4490_7_testbench/f2
add wave -position end  sim:/jyh_4490_7_testbench/p
add wave -position end  sim:/jyh_4490_7_testbench/sta
run -all
# Compile of jyh_4490_7_is.v was successful.
vsim work.jyh_4490_7_testbench
# running
vsim work.jyh_4490_7_testbench
# running
vsim work.jyh_4490_7_testbench
# running
vsim work.jyh_4490_7_testbench
# running
vsim work.jyh_4490_7_testbench
# running
vsim work.jyh_4490_7_testbench
# running
vsim work.jyh_4490_7_testbench
# running
vsim work.jyh_4490_7_testbench
# running
restart -f
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# Loading work.jyh_4490_7_is
restart
run -all
# End time: 22:26:44 on May 17,2022, Elapsed time: 0:43:03
# Errors: 0, Warnings: 1