module design(
	input wire clk,//50MHz时钟
	output reg led, //用于指示
	input wire rst_n,
	input wire rxd,
	output wire txd,
	inout dht_io
);

	reg [31:0]cnt;
	reg led_f1,tx_flag;
	always@(posedge clk)
	begin
		led_f1 <= led;
		tx_flag <= led &(~led_f1);
		if(cnt >= 32'd25000000 - 1)
		begin
			cnt <= 0;
			led <=~led;
		end
		else begin
			cnt <= cnt + 1'b1 ;
		end
	end
	//--------------------------------------------
	localparam s_s1=0;
	localparam s_s2=1;
	localparam s_s3=2;
	localparam s_s4=3;
	reg [7:0]send_data;
	reg to_uart_valid , to_uart_ready;
	reg [2:0]send_st;
	reg [7:0]data_cnt;
	always@(posedge clk)
	begin
		if(!rst_n)begin
			to_uart_ready <= 1'b0;
			to_uart_valid <= 1'b0;
			send_data <= 8'd0;
			send_st<= s_s1;
			data_cnt <= 8'd0;
		end
		
		else begin
			case(send_st)
				s_s1:begin//待机
						if(tx_flag)begin
							send_st <= s_s2;
							to_uart_valid <= 1'b0;
							to_uart_ready<= 1'b0;
							data_cnt <= 8'd0;
							send_data <= 9;
						end
						else begin
							to_uart_valid <= 1'b0;
							to_uart_ready<= 1'b0;
						end
					end
				s_s2:begin
						if(data_cnt <= 8'd8-1'b1)begin
							to_uart_valid <= 1'b1;
							send_data <= data_cnt+1;
							data_cnt <= data_cnt + 1'b1;
							send_st <= (data_cnt >= 8'd5-1)?s_s3:s_s2;
						end
					end
				s_s3:begin
						to_uart_valid <= 1'b0;
						to_uart_ready <= 1'b1;
						send_st <= s_s1;
						data_cnt<=8'd0;
					end
				default :send_st <= s_s1;
			endcase
		end
	end
	
uart_screen u0 (
        .rs232_0_to_uart_data    (send_data),    //  rs232_0_avalon_data_transmit_sink.data
        .rs232_0_to_uart_error   (),   //                                   .error
        .rs232_0_to_uart_valid   (to_uart_valid),   //                                   .valid
        .rs232_0_to_uart_ready   (to_uart_ready),   //                                   .ready
        .rs232_0_UART_RXD        (rxd),        //         rs232_0_external_interface.RXD
        .rs232_0_UART_TXD        (txd),        //                                   .TXD
        .clk_clk                 (clk),                 //                                clk.clk
        .reset_reset_n           (rst_n)            //                              reset.reset_n
    );
	
	
	
endmodule