module jyh_4490_5_divider(clk_out,sel,clk,en);
	input clk,sel,en;
	output reg clk_out;
	reg [14:0]counter=0;
   localparam TARGET_4=2784;   // ((1/4490)/(1/50M))/4
	localparam TARGET_5=863;		// ((1/14490)/(1/50M))/4


   initial begin
      clk_out=0;
	end
   always @(posedge clk)
	if(en)
	begin
      counter<=counter+1;
		if(sel)
		begin
			if(counter==TARGET_5)		
			begin
				clk_out<=0;
			end
			if(counter==4*TARGET_5)
			begin
				clk_out<=1;
				counter<=0;
			end
		end

		else if(!sel)
		begin
			if(counter==TARGET_4)
				begin
					clk_out<=0;
				end
			if(counter==4*TARGET_4)
				begin
					clk_out<=1;
					counter<=0;
				end
		end
	end
endmodule