//译码器模块
module jyh_4490_2_2(out,in);
	input[2:0] in;
	output[6:0] out;
	
	reg[7:0] out;
	
always @ (in)
 	begin
		case (in)
		3'd0: out<=7'b0000001;
		3'd1: out<=7'b0000011;
		3'd2: out<=7'b0000111;
		3'd3: out<=7'b0001111;
		3'd4: out<=7'b0011111;
		3'd5: out<=7'b0111111;
	   3'd6: out<=7'b0000000;

		default:		out=7'bx;
		endcase
	end
endmodule