UART

2022.05.24.19:47:23 Datasheet
Overview
  clk_0  UART

Memory Map

clk_0

clock_source v21.1


Parameters

clockFrequency 5000000
clockFrequencyKnown true
inputClockFrequency 0
resetSynchronousEdges NONE
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

rs232_0

altera_up_avalon_rs232 v17.1


Parameters

ref_clk_freq 0.0
avalon_bus_type Streaming
baud 115200
parity None
data_bits 8
stop_bits 1
AUTO_DEVICE_FAMILY CYCLONEIVE
AUTO_CLK_CLOCK_RATE 0
deviceFamily Cyclone IV E
generateLegacySim false
  

Software Assignments

(none)
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