module jyh_4490_4_divider(clk,clk_out);
	 input clk;
	 output reg clk_out;
    localparam TARGET=2;
    reg [15:0]counter=0; 
    initial begin
        clk_out=0;
    end
    always @(posedge clk)
	 begin
        counter=counter+1;
        if(counter==TARGET)
			begin
            counter=0;
            clk_out=!clk_out;
        end
    end
endmodule