// UART.v // Generated using ACDS version 21.1 842 `timescale 1 ps / 1 ps module UART ( input wire clk_clk, // clk.clk input wire reset_reset_n, // reset.reset_n input wire rs232_0_from_uart_ready, // rs232_0_avalon_data_receive_source.ready output wire [7:0] rs232_0_from_uart_data, // .data output wire rs232_0_from_uart_error, // .error output wire rs232_0_from_uart_valid, // .valid input wire [7:0] rs232_0_to_uart_data, // rs232_0_avalon_data_transmit_sink.data input wire rs232_0_to_uart_error, // .error input wire rs232_0_to_uart_valid, // .valid output wire rs232_0_to_uart_ready, // .ready input wire rs232_0_clk, // rs232_0_clk.clk input wire rs232_0_UART_RXD, // rs232_0_external_interface.RXD output wire rs232_0_UART_TXD, // .TXD input wire rs232_0_reset // rs232_0_reset.reset ); UART_rs232_0 rs232_0 ( .clk (rs232_0_clk), // clk.clk .reset (rs232_0_reset), // reset.reset .from_uart_ready (rs232_0_from_uart_ready), // avalon_data_receive_source.ready .from_uart_data (rs232_0_from_uart_data), // .data .from_uart_error (rs232_0_from_uart_error), // .error .from_uart_valid (rs232_0_from_uart_valid), // .valid .to_uart_data (rs232_0_to_uart_data), // avalon_data_transmit_sink.data .to_uart_error (rs232_0_to_uart_error), // .error .to_uart_valid (rs232_0_to_uart_valid), // .valid .to_uart_ready (rs232_0_to_uart_ready), // .ready .UART_RXD (rs232_0_UART_RXD), // external_interface.export .UART_TXD (rs232_0_UART_TXD) // .export ); endmodule