`timescale 1ns/1ns
module tb;
reg clk;
reg key;
wire [3:0] out;

initial begin
	clk=0;
	key=0;
end

always#10 clk=~clk;
always begin
repeat(10)
#15 key=~key;

repeat(10)
#15 key=0;
end
	
mstate M1(
.clk(clk),
.key(key),
.out(out));

endmodule