36 lines
1.9 KiB
Text
36 lines
1.9 KiB
Text
Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --block-symbol-file --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART --family="Cyclone IV E" --part=EP4CE6E22C8
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Progress: Loading Design/UART.qsys
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Progress: Reading input file
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Progress: Adding clk_0 [clock_source 21.1]
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Progress: Parameterizing module clk_0
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Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
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Progress: Parameterizing module rs232_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem.
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Info: qsys-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate /home/ir/Documents/codelib/Quartus/Design/UART.qsys --synthesis=VERILOG --output-directory=/home/ir/Documents/codelib/Quartus/Design/UART/synthesis --family="Cyclone IV E" --part=EP4CE6E22C8
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Progress: Loading Design/UART.qsys
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Progress: Reading input file
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Progress: Adding clk_0 [clock_source 21.1]
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Progress: Parameterizing module clk_0
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Progress: Adding rs232_0 [altera_up_avalon_rs232 17.1]
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Progress: Parameterizing module rs232_0
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Warning: UART.clk_0: The input clock frequency must be known or set by the parent if this is a subsystem.
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Info: UART: Generating UART "UART" for QUARTUS_SYNTH
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Info: rs232_0: Starting Generation of RS232 UART
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Error: rs232_0: The input clock frequency must be known at generation time.
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Info: rs232_0: "UART" instantiated altera_up_avalon_rs232 "rs232_0"
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Info: UART: Done "UART" with 2 modules, 6 files
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Error: qsys-generate failed with exit code 1: 1 Error, 1 Warning
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Info: Finished: Create HDL design files for synthesis
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