71 lines
779 B
Verilog
71 lines
779 B
Verilog
module jyh_4490_mstate(clk,in,en,out,cnt);
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input clk,in,en;
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output reg out;
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output reg [19:0] cnt=0;
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reg[1:0] state=0;
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parameter s0=0,s1=1,s2=2,s3=3;
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parameter TARGET=750000; //50mhz 15ms
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always @(posedge clk)
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if(!en)
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state=s0;
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else
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case(state)
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s0:
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begin
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out=0;
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cnt=0;
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if(in)
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state=s1;
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end
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s1:
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begin
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out=0;
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if(cnt<TARGET)
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begin
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state=s1;
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cnt=cnt+1;
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end
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else
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begin
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cnt=0;
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if(in)
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state=s2;
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else
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state=s0;
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end
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end
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s2:
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begin
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out=1;
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cnt=0;
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if(!in)
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state=s3;
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end
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s3:
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begin
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out=1;
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if(cnt<TARGET)
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begin
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state=s3;
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cnt=cnt+1;
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end
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else
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begin
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cnt=0;
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if(in)
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state=s2;
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else
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state=s0;
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end
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end
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default:
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begin
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state=s0;
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out=0;
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cnt=0;
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end
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endcase
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endmodule
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